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| ISP1161A Full-speed Universal Serial Bus single-chip host and device controller Rev. 01 -- 02 August 2002 Product data 1. General description The ISP1161A is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC) that complies with Universal Serial Bus Specification Rev. 2.0 (full speed and low speed). These two USB controllers, the HC and the DC, share the same microprocessor bus interface. They have the same data bus, but different I/O locations. They also have separate interrupt request output pins, separate DMA channels that include separate DMA request output pins and DMA acknowledge input pins. This makes it possible for a microprocessor to control both the USB HC and the USB DC at the same time. ISP1161A provides two downstream ports for the USB HC and one upstream port for the USB DC. Each downstream port has an overcurrent (OC) detection input pin and power supply switching control output pin. The upstream port has a VBUS detection input pin. ISP1161A also provides separate wake-up input pins and suspended status output pins for the USB HC and the USB DC, respectively. This makes power management flexible. The downstream ports for the HC can be connected with any USB compliant devices and hubs that have USB upstream ports. The upstream port for the DC can be connected to any USB compliant USB host and USB hubs that have USB downstream ports. The HC is adapted from the Open Host Controller Interface Specification for USB Release 1.0a, referred to as OHCI in the rest of this document. The DC is compliant with most USB device class specifications such as Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices and Human Interface Devices. ISP1161A is well suited for embedded systems and portable devices that require a USB host only, a USB device only, or a combination of a configurable USB host and USB device. ISP1161A brings high flexibility to the systems that have it built-in. For example, a system that uses an ISP1161A allows it not only to be connected to a PC or USB hub with a USB downstream port, but also to be connected to a device that has a USB upstream port such as a USB printer, USB camera, USB keyboard or a USB mouse. Therefore, the ISP1161A enables peer-to-peer connectivity between embedded systems. An interesting application example is to connect an ISP1161A HC with an ISP1161A DC. Consider an example of an ISP1161A being used in a Digital Still Camera (DSC) design. Figure 1 shows an ISP1161A being used as a USB DC. Figure 2 shows an ISP1161A being used as a USB HC. Figure 3 shows an ISP1161A being used as a USB HC and a USB DC at the same time. Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller EMBEDDED SYSTEM P P SYSTEM MEMORY PC (host) P bus I/F ISP1161A HOST/ DEVICE USB cable USB I/F USB I/F USB device DSC 004aaa080 Fig 1. ISP1161A operating as a USB device. EMBEDDED SYSTEM P P SYSTEM MEMORY P bus I/F ISP1161A HOST/ DEVICE USB cable USB I/F PRINTER (device) USB I/F DSC USB host 004aaa081 Fig 2. ISP1161A operating as a stand-alone USB host. EMBEDDED SYSTEM P P SYSTEM MEMORY PC (host) P bus I/F DSC PRINTER (device) ISP1161A HOST/ DEVICE USB cable USB I/F USB device USB host 004aaa082 USB cable USB I/F USB I/F USB I/F Fig 3. ISP1161A operating as both USB host and device simultaneously. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 2 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 2. Features s Complies with Universal Serial Bus Specification Rev. 2.0 (full speed and low speed) s Combines the HC and the DC in a single chip s On-chip DC complies with most USB device class specifications s Both the HC and the DC can be accessed by an external microprocessor via separate I/O port addresses s Selectable one or two downstream ports for the HC and one upstream port for the DC s High-speed parallel interface to most generic microprocessors and Reduced Instruction Set Computer (RISC) processors (HitachiTM SH3 and SH4, MIPS-based RISC, ARM(R)7/9, StrongARM(R), etc.) s Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC, 11.1 Mbyte/s data transfer rate between the microprocessor and the DC s Supports single-cycle and burst mode DMA operations s Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints for the DC s Built-in separate FIFO buffer RAM for the HC (4 kbytes) and DC (2462 bytes) s Endpoints with double buffering to increase throughput and ease real-time data transfer for both DC transfers and HC isochronous (ISO) transactions s 6 MHz crystal oscillator with integrated PLL for low EMI s Controllable LazyClock (100 50% kHz) output during `suspend' s Clock output with programmable frequency (3 to 48 MHz) s Software controlled connection to the USB bus (SoftConnectTM) on upstream port for the DC s Good USB connection indicator that blinks with traffic (GoodLinkTM) for the DC s Software selectable internal 15 k pull-down resistors for HC downstream ports s Dedicated pins for suspend sensing output and wake-up control input for flexible applications s Global hardware reset input pin and separate internal software reset circuits for HC and DC s Operation from a +5 V or a +3.3 V power supply s 8 kV in-circuit ESD protection s Operating temperature range -40 to +85 C s Available in two LQFP64 packages (SOT314-2 and SOT414-1). 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 3 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 3. Applications s s s s s s s s Personal Digital Assistant (PDA) Digital camera Third-generation (3-G) phone Set-top box (STB) Information Appliance (IA) Photo printer MP3 jukebox Game console. 4. Ordering information Table 1: Ordering information Package Name ISP1161ABD ISP1161ABM LQFP64 LQFP64 Description Plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm Plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm Version SOT314-2 SOT414-1 Type number 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 4 of 132 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data Rev. 01 -- 02 August 2002 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09568 5. Block diagram Philips Semiconductors 6 MHz to/ from microprocessor H_WAKEUP H_SUSPEND NDP_SEL 40 42 33 2 to 7, 9 to 14, 16, 17, 63, 64 22 21 23 60 59 28 27 34 26 25 30 29 ALT RAM ITL0 (PING RAM) ITL1 (PONG RAM) HOST CONTROLLER XTAL2 44 XTAL1 43 46 47 54 55 H_PSW1 H_PSW2 H_OC1 H_OC2 POWER SWITCHING OVERCURRENT DETECTION 16 D0 to D15 RD CS WR A1 A0 DACK2 DACK1 EOT DREQ2 DREQ1 INT2 INT1 ISP1161A PHILIPS SLAVE HOST CONTROLLER HOST/ DEVICE AUTOMUX 50 USB TRANSCEIVER USB TRANSCEIVER 51 52 53 H_DM1 H_DP1 H_DM2 H_DP2 USB bus downstream ports HOST BUS INTERFACE Host bus CLOCK RECOVERY PLL 4x 15 k Full-speed USB single-chip host and device controller DEVICE BUS INTERFACE Device bus CLOCK RECOVERY GND 39 USB TRANSCEIVER 48 49 D_WAKEUP D_SUSPEND 37 36 DEVICE CONTROLLER D_VBUS D_DM D_DP USB bus upstream port RESET 32 POWER-ON RESET internal reset PING RAM PONG RAM SoftConnect 1.5 k 3.3 V DEVICE CONTROLLER GoodLink 38 PROGRAMMABLE DIVIDER 41 61, 20 VCC 56 VOLTAGE REGULATOR 1, 8, 15, 18, 35, 45, 62 7 3.3 V internal supply 57 58 24 19 DGND AGND Vreg(3.3) 2 GL CLKOUT n.c. 004aaa083 Vhold1 Vhold2 ISP1161A 5 of 132 Fig 4. Block diagram. Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller POWER-ON RESET Memory block ATL RAM Philips sHC core USB STATE USB Interface clock recovery P interface DMA HANDLER Host bus I/F BUS I/F ITL0 RAM ITL1 RAM MEMORY MANAGEMENT UNIT P HANDLER FRAME MANAGEMENT REGISTER ACCESS PDT_LIST PROCESS PHILIPS SIE USB bus USB TRANSCEIVER H_DP1 H_DM1 H_DP2 H_DM2 Host controller sub-blocks MGT930 Fig 5. Host controller sub-block diagram. POWER-ON RESET SoftConnect DMA HANDLER INTEGRATED RAM 3.3 V USB bus Device bus I/F BUS I/F P HANDLER MEMORY MANAGEMENT UNIT PHILIPS SIE USB TRANSCEIVER D_DP D_DM clock recovery EP HANDLER Device controller sub-blocks GoodLink MGT931 GL Fig 6. Device controller sub-block diagram. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 6 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 6. Pinning information 6.1 Pinning 58 Vreg(3.3) 52 H_DM2 50 H_DM1 55 H_OC2 54 H_OC1 53 H_DP2 51 H_DP1 62 DGND 57 AGND DGND 1 D2 2 D3 3 D4 4 D5 5 D6 6 D7 7 DGND 8 D8 9 D9 10 D10 11 D11 12 D12 13 D13 14 DGND 15 D14 16 n.c. 20 CS 21 RD 22 WR 23 Vhold2 24 DREQ1 25 DREQ2 26 DACK1 27 DACK2 28 INT1 29 INT2 30 TEST 31 RESET 32 D15 17 DGND 18 Vhold1 19 56 VCC 61 n.c. 64 D1 63 D0 60 A1 59 A0 49 D_DP 48 D_DM 47 H_PSW2 46 H_PSW1 45 DGND 44 XTAL2 43 XTAL1 42 H_SUSPEND ISP1161ABD ISP1161ABM 41 CLKOUT 40 H_WAKEUP 39 D_VBUS 38 GL 37 D_WAKEUP 36 D_SUSPEND 35 DGND 34 EOT 33 NDP_SEL 004aaa085 Fig 7. Pin configuration LQFP64. 6.2 Pin description Table 2: Symbol[1] DGND D2 D3 D4 D5 Pin description for LQFP64 Pin 1 2 3 4 5 Type I/O I/O I/O I/O Description digital ground bit 2 of bidirectional data; slew-rate controlled; TTL input; three-state output bit 3 of bidirectional data; slew-rate controlled; TTL input; three-state output bit 4 of bidirectional data; slew-rate controlled; TTL input; three-state output bit 5 of bidirectional data; slew-rate controlled; TTL input; three-state output 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 7 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Pin description for LQFP64 ...continued Pin 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description bit 6 of bidirectional data; slew-rate controlled; TTL input; three-state output bit 7 of bidirectional data; slew-rate controlled; TTL input; three-state output digital ground bit 8 of bidirectional data; slew-rate controlled; TTL input; three-state output bit 9 of bidirectional data; slew-rate controlled; TTL input; three-state output bit 10 of bidirectional data; slew-rate controlled; TTL input; three-state output bit 11 of bidirectional data; slew-rate controlled; TTL input; three-state output bit 12 of bidirectional data; slew-rate controlled; TTL input; three-state output bit 13 of bidirectional data; slew-rate controlled; TTL input; three-state output digital ground bit 14 of bidirectional data; slew-rate controlled; TTL input; three-state output bit 15 of bidirectional data; slew-rate controlled; TTL input; three-state output digital ground voltage holding pin; internally connected to the Vreg(3.3) and Vhold2 pins. When VCC is connected to +5 V, this pin will output 3.3 V, hence do not connect it to +5 V. When VCC is connected to +3.3 V, this pin can either be connected to +3.3 V or left unconnected. In all cases, decouple this pin to DGND. no connection chip select input read strobe input write strobe input voltage holding pin; internally connected to the Vreg(3.3) and Vhold1 pins. When VCC is connected to +5 V, this pin will output 3.3 V, hence do not connect it to +5 V. When VCC is connected to +3.3 V, this pin can either be connected to +3.3 V or left unconnected. In all cases, decouple this pin to DGND. HC DMA request output (programmable polarity); signals to the DMA controller that the ISP1161A wants to start a DMA transfer; see Section 10.4.1 DC DMA request output (programmable polarity); signals to the DMA controller that the ISP1161A wants to start a DMA transfer; see Section 13.1.4 HC DMA acknowledge input; when not in use, this pin must be connected to VCC via an external 10 k resistor (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Table 2: Symbol[1] D6 D7 DGND D8 D9 D10 D11 D12 D13 DGND D14 D15 DGND Vhold1 n.c. CS RD WR Vhold2 20 21 22 23 24 I I I - DREQ1 25 O DREQ2 26 O DACK1 27 I 9397 750 09568 Product data Rev. 01 -- 02 August 2002 8 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Pin description for LQFP64 ...continued Pin 28 29 30 31 32 33 Type I O O O I I Description DC DMA acknowledge input; when not in use, this pin must be connected to VCC via an external 10 k resistor HC interrupt output; programmable level, edge triggered and polarity; see Section 10.4.1 DC interrupt output; programmable level, edge triggered and polarity; see Section 13.1.4 test output; used for test purposes only; this pin is not connected during normal operation reset input (Schmitt trigger); a LOW level produces an asynchronous reset indicates to the HC software the Number of Downstream Ports (NDP) present: 0 -- select 1 downstream port 1 -- select 2 downstream ports only changes the value of the NDP field in the HcRhDescriptorA Register; both ports will always be enabled; see Section 10.3.1 Table 2: Symbol[1] DACK2 INT1 INT2 TEST RESET NDP_SEL EOT DGND D_SUSPEND D_WAKEUP 34 35 36 37 I O I DMA master device to inform the ISP1161A of end of DMA transfer; active level is programmable; see Section 10.4.1 digital ground DC `suspend' state indicator output; active HIGH DC wake-up input; generates a remote wake-up from `suspend' state (active HIGH); when not in use, this pin must be connected to DGND via an external 10 k resistor GoodLink LED indicator output (open-drain, 8 mA); the LED is default ON, blinks OFF upon USB traffic; to connect an LED use a series resistor of 470 (VCC = 5.0 V) or 330 (VCC = 3.3 V) DC USB upstream port VBUS sensing input; when not in use, this pin must be connected to DGND via a 1 M resistor HC wake-up input; generates a remote wake-up from `suspend' state (active HIGH); when not in use, this pin must be connected to DGND via an external 10 k resistor programmable clock output (3 to 48 MHz); default 12 MHz HC `suspend' state indicator output; active HIGH crystal input; connected directly to a 6 MHz crystal; when XTAL1 is connected to an external clock source, pin XTAL2 must be left open crystal output; connected directly to a 6 MHz crystal; when pin XTAL1 is connected to an external clock source, this pin must be left open digital ground power switching control output for downstream port 1; open drain output GL 38 O D_VBUS 39 I H_WAKEUP 40 I CLKOUT H_SUSPEND XTAL1 41 42 43 O O I XTAL2 44 O DGND H_PSW1 45 46 O 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 9 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Pin description for LQFP64 ...continued Pin 47 48 49 50 51 52 53 54 55 56 Type O AI/O AI/O AI/O AI/O AI/O AI/O I I Description power switching control output for downstream port 2; open drain output USB D- data line for DC upstream port; when not in use, this pin must be left open USB D+ data line for DC upstream port; when not in use, this pin must be left open USB D- data line for HC downstream port 1 USB D+ data line for HC downstream port 1 USB D- data line for HC downstream port 2; when not in use, this pin must be left open USB D+ data line for HC downstream port 2; when not in use, this pin must be left open overcurrent sensing input for HC downstream port 1 overcurrent sensing input for HC downstream port 2 power supply voltage input (3.0 to 3.6 V or 4.75 to 5.25 V). This pin connects to the internal 3.3 V regulator input. When connected to +5 V, the internal regulator will output 3.3 V to pins Vreg(3.3), Vhold1 and Vhold2. When connected to 3.3 V, it will bypass the internal regulator. analog ground internal 3.3 V regulator output; when the VCC pin is connected to +5 V, this pin outputs 3.3 V. When the VCC pin is connected to +3.3 V, connect this pin to +3.3 V. address input; selects command (A0 = 1) or data (A0 = 0) address input; selects AutoMux switching to DC (A1 = 1) or AutoMux switching to HC (A1 = 0); see Table 3 no connection digital ground bit 0 of bidirectional data; slew-rate controlled; TTL input; three-state output bit 1 of bidirectional data; slew-rate controlled; TTL input; three-state output Table 2: Symbol[1] H_PSW2 D_DM D_DP H_DM1 H_DP1 H_DM2 H_DP2 H_OC1 H_OC2 VCC AGND Vreg(3.3) 57 58 - A0 A1 n.c. DGND D0 D1 59 60 61 62 63 64 I I I/O I/O [1] Symbol names with an overscore (e.g. NAME) represent active LOW signals. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 10 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 7. Functional description 7.1 PLL clock multiplier A 6 to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external components are required for the operation of the PLL. 7.2 Bit clock recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream using a 4 times over-sampling principle. It is able to track jitter and frequency drift as specified in the Universal Serial Bus Specification Rev. 2.0. 7.3 Analog transceivers Three sets of transceivers are embedded in the chip: two are used for downstream ports with USB connector type A; one is used for upstream port with USB connector type B. The integrated transceivers are compliant with the Universal Serial Bus Specification Rev. 2.0. They interface directly with the USB connectors and cables through external termination resistors. 7.4 Philips Serial Interface Engine (SIE) The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit (de)stuffing, CRC checking/generation, Packet IDentifier (PID) verification/generation, address recognition, handshake evaluation/generation. There are separate SIEs in the HC and the DC. 7.5 SoftConnect The connection to the USB is accomplished by bringing D+ (for full-speed USB devices) HIGH through a 1.5 k pull-up resistor. In the ISP1161A DC, the 1.5 k pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established through a command sent by the external/system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the USB. Re-initialization of the USB connection can also be performed without disconnecting the cable. The ISP1161A DC will check for USB VBUS availability before the connection can be established. VBUS sensing is provided through pin D_VBUS. Remark: The tolerance of the internal resistors is 25%. This is higher than the 5% tolerance specified by the USB specification. However, the overall VSE voltage specification for the connection can still be met with a good margin. The decision to make use of this feature lies with the USB equipment designer. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 11 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 7.6 GoodLink Indication of a good USB connection is provided at pin GL through GoodLink technology. During enumeration, the LED indicator will blink on momentarily. When the DC has been successfully enumerated (the device address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1161A the LED will blink off for 100 ms. During `suspend' state the LED will remain off. This feature provides a user-friendly indication of the status of the USB device, the connected hub and the USB traffic. It is a useful field diagnostics tool for isolating faulty equipment. It can therefore help to reduce field support and hotline overhead. 8. Microprocessor bus interface 8.1 Programmed I/O (PIO) addressing mode A generic PIO interface is defined for speed and ease-of-use. It also allows direct interfacing to most microcontrollers. To a microcontroller, the ISP1161A appears as a memory device with a 16-bit data bus and uses only two address lines: A1 and A0 to access the internal control registers and FIFO buffer RAM. Therefore, the ISP1161A occupies only four I/O ports or four memory locations of a microprocessor. External microprocessors can read from or write to the ISP1161A internal control registers and FIFO buffer RAM through the Programmed I/O (PIO) operating mode. Figure 8 shows the Programmed I/O interface between a microprocessor and an ISP1161A. P bus I/F D [15:0] RD WR MICROPROCESSOR CS A2 A1 IRQ1 IRQ2 D [15:0] RD WR CS A1 A0 INT1 INT2 004aaa086 ISP1161A Fig 8. Programmed I/O interface between a microprocessor and an ISP1161A. 8.2 DMA mode The ISP1161A also provides DMA mode for external microprocessors to access its internal FIFO buffer RAM. Data can be transferred by DMA operation between a microprocessor's system memory and the ISP1161A internal FIFO buffer RAM. Remark: The DMA operation must be controlled by the external microprocessor system DMA controller (Master). 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 12 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Figure 9 shows the DMA interface between a microprocessor system and the ISP1161A. The ISP1161A provides two DMA channels: * DMA channel 1 (controlled by DREQ1, DACK1 signals) is for the DMA transfer between a microprocessor's system memory and ISP1161A HC internal FIFO buffer RAM. * DMA channel 2 (controlled by DREQ2, DACK2 signals) is for the DMA transfer between a microprocessor system memory and the ISP1161A DC internal FIFO buffer RAM The EOT signal is an external end-of-transfer signal used to terminate the DMA transfer. Some microprocessors may not have this signal. In this case, the ISP1161A provides an internal EOT signal to terminate the DMA transfer as well. Setting the HcDMAConfiguration Register (21H - read, A1H - write) enables the ISP1161A HC internal DMA counter for DMA transfer. When the DMA counter reaches the value set in the HcTransferCounter Register (22H - read, A2H - write), an internal EOT signal will be generated to terminate the DMA transfer. P bus I/F D [15:0] RD WR MICROPROCESSOR DACK1 DREQ1 DACK2 DREQ2 EOT D [15:0] RD WR DACK1 DREQ1 DACK2 DREQ2 EOT 004aaa087 ISP1161A Fig 9. DMA interface between a microprocessor and an ISP1161A. 8.3 Control register access by PIO mode 8.3.1 I/O port addressing Table 3 shows the ISP1161A I/O port addressing. Complete decoding of the I/O port address should include the chip select signal CS and the address lines A1 and A0. However, the direction of the access of the I/O ports is controlled by the RD and WR signals. When RD is LOW, the microprocessor reads data from the ISP1161A data port. When WR is LOW, the microprocessor writes a command to the command port, or writes data to the data port. Table 3: Port 0 1 2 3 9397 750 09568 I/O port addressing CS 0 0 0 0 A1,A0 (Bin) 00 01 10 11 Access R/W W R/W W Data bus width (bits) 16 16 16 16 Description HC data port HC command port DC data port DC command port (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 13 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Figure 10 and Figure 11 illustrate how an external microprocessor accesses the ISP1161A internal control registers. AUTOMUX DC/HC 0 P bus I/F Device bus I/F 1 A1 Host bus I/F MGT935 When A1 = 0, the microprocessor accesses the HC. When A1 = 1, the microprocessor accesses the DC. Fig 10. Microprocessor access to a HC or a DC via an automux switch. CMD/DATA SWITCH Host or Device bus I/F 1 command port data port 0 A0 Commands . . . Control registers Command register MGT936 When A0 = 0, the microprocessor accesses the data port. When A0 = 1, the microprocessor accesses the command port. Fig 11. Microprocessor access to internal control registers. 8.3.2 Register access phases The ISP1161A register structure is a command-data register pair structure. A complete register access cycle comprises a command phase followed by a data phase. The command (also known as the index of a register) points the ISP1161A to the next register to be accessed. A command is 8 bits long. On a microprocessor's 16-bit data bus, a command occupies the lower byte, with the upper byte filled with zeros. Figure 12 shows a complete 16-bit register access cycle for the ISP1161A. The microprocessor writes a command code to the command port, and then reads or writes the data word from or to the data port. Take the example of a microprocessor attempting to read the ISP1161A's ID. The ID is kept in the HC's HcChipID Register (index 27H, read only). The 16-bit register access cycle is therefore: 1. Microprocessor writes the command code of 27H (0027H in 16-bit width) to the HC command port 2. Microprocessor reads the data word of the chip's ID (6110H for engineering sample; version one) from the HC data port. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 14 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 16-bit register access cycle write command (16 bits) read/write data (16 bits) t MGT937 Fig 12. 16-bit register access cycle. Most of the ISP1161A internal control registers are 16 bits wide. Some of the internal control registers have 32-bit width. Figure 13 shows how the 32-bit internal control register is accessed. The complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. In the two data phases, the microprocessor first reads or writes the lower 16-bits, followed by the upper 16-bits. 32-bit register access cycle write command (16 bits) read/write data (lower 16 bits) read/write data (upper 16 bits) t MGT938 Fig 13. 32-bit register access cycle. To further describe the complete access cycles of the internal control registers, the status of some pins of the microprocessor bus interface are shown in Figure 14 and Figure 15 for the HC and the DC respectively. CS A1, A0 01 00 00 read WR write write write RD read read write write read D [15:0 ] HC command code HC register data (lower word) HC register data (upper word) MGT939 Fig 14. Accessing HC control registers. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 15 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller CS A1, A0 11 10 read 10 read write write read WR write write write RD read D [15:0 ] DC command code DC register data (lower word) DC register data (upper word) MGT940 Fig 15. Accessing DC control registers. 8.4 FIFO buffer RAM access by PIO mode Since the ISP1161A internal memory is structured as a FIFO buffer RAM, the FIFO buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal FIFO buffer RAM is similar to accessing the internal control registers in multiple data phases. FIFO buffer RAM access cycle (transfer counter = 2N) write command (16 bits) read/write data #1 (16 bits) read/write data #2 (16 bits) read/write data #N (16 bits) t MGT941 Fig 16. Internal FIFO buffer RAM access cycle. Figure 16 shows a complete access cycle of the HC internal FIFO buffer RAM. For a write cycle, the microprocessor first writes the FIFO buffer RAM's command code to the command port, and then writes the data words one by one to the data port until half of the transfer's byte count is reached. The HcTransferCounter Register (22H read, A2H - write) is used to specify the byte count of a FIFO buffer RAM's read cycle or write cycle. Every access cycle must be in the same access direction. The read cycle procedure is similar to the write cycle. For access to the DC FIFO buffer RAM access, see Section 13. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 16 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 8.5 FIFO buffer RAM access by DMA mode The DMA interface between a microprocessor and the ISP1161A is shown in Figure 9. When doing a DMA transfer, at the beginning of every burst the ISP1161A outputs a DMA request to the microprocessor via the DREQ pin (DREQ1 for HC, DREQ2 for DC). After receiving this signal, the microprocessor will reply with a DMA acknowledge via the DACK pin (DACK1 for HC, DACK2 for DC), and at the same time, execute the DMA transfer through the data bus. In the DMA mode, the microprocessor must issue a read or write signal to the ISP1161A RD or WR pin. The ISP1161A will repeat the DMA cycles until it receives an EOT signal to terminate the DMA transfer. ISP1161A supports both external and internal EOT signals. The external EOT signal is received as input on pin EOT, and generally comes from the external microprocessor. The internal EOT signal is generated by the ISP1161A internally. To select either EOT method, set the appropriate DMA configuration register (see Section 10.4.2 and Section 13.1.6). For example, for the HC, setting DMACounterSelect bit of the HcDMAConfiguration Register (21H - read, A1H - write) to logic 1 will enable the DMA counter for DMA transfer. When the DMA counter reaches the value of the HcTransferCounter Register, the internal EOT signal will be generated to terminate the DMA transfer. ISP1161A supports either single-cycle DMA operation or burst mode DMA operation. DREQ DACK RD or WR D [15:0 ] data #1 EOT 004aaa103 data #2 data #N N = 1/2 byte count of transfer data. Fig 17. DMA transfer in single-cycle mode. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 17 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller DREQ DACK RD or WR D [15:0 ] data #1 EOT 004aaa104 data #K data #(K+1) data #2K data #(N-K+1) data #N N = 1/2 byte count of transfer data, K = number of cycles/burst. Fig 18. DMA transfer in burst mode. In Figure 17 and Figure 18, the hardware is configured such that DREQ is active HIGH and DACK is active LOW. 8.6 Interrupts The ISP1161A has separate interrupt request pins for the USB HC (INT1) and the USB DC (INT2). 8.6.1 Pin configuration The interrupt output signals have four configuration modes: Mode 0 Mode 1 Mode 2 Mode 3 Level trigger, active LOW (default at power-up) Level trigger, active HIGH Edge trigger, active LOW Edge trigger, active HIGH. Figure 19 shows these four interrupt configuration modes. They are programmable via the HcHardwareConfiguration Register (see Section 10.4.1), which are also used to disable or enable the signals. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 18 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller INT active INT clear or disable INT Mode 0 level triggered, active LOW INT active INT Mode 1 level triggered, active HIGH INT active INT 166 ns Mode 2 edge triggered, active LOW INT active INT 166 ns Mode 3 edge triggered, active HIGH MGT944 clear or disable INT Fig 19. Interrupt pin operating modes. 8.6.2 HC's interrupt output pin (INT1) To program the four configuration modes of the HC's interrupt output signal (INT1), set bits InterruptPinTrigger and InterruptOutputPolarity of the HcHardwareConfiguration Register (20H - read, A0H - write). Bit InterruptPinEnable is used as the master enable setting for pin INT1. INT1 has many associated interrupt events, as shown as in Figure 20. The interrupt events of the HcPInterrupt Register (24H - read, A4H - write) changes the status of pin INT1 when the corresponding bits of the HcPInterruptEnable Register (25H - read, A5H - write) and pin INT1's global enable bit (InterruptPinEnable of the HcHardwareConfiguration Register) are all set to enable status. However, events that come from the HcInterruptStatus Register (03H - read, 83H write) affect only the OPR_Reg bit of the HcPInterrupt Register. They cannot directly change the status of pin INT1. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 19 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcInterruptStatus register SO SF RD UE FNO RHSC X HcuPInterrupt register SOF/ITL ATL All EOT OPR Reg HcSuspend ClkReady INT Enable SO IE SF IE RD IE UE IE FNO IE RHSC IE HcInterruptEnable register X SOF/ITL IE ATL IE All EOT IE OPR Reg IE HcSuspend IE ClkReady IE HcuPInterruptEnable register HcHardwareConfiguration register INT Trigger INT Polarity PULSE GENERATOR . . . 1 0 INT1 MGT945 Fig 20. HC interrupt logic. 8.6.3 DC interrupt output pin (INT2) The four configuration modes of DC's interrupt output pin INT2 can also be programmed by setting bits INTPOL and INTLVL of the DcHardwareConfiguration Register (BBH - read, BAH - write). Bit INTENA of the DcMode Register (B9H - read, B8H - write) is used to enable pin INT2. Figure 21 shows the relationship between the interrupt events and pin INT2. Each of the indicated USB events is logged in a status bit of the DcInterrupt Register. Corresponding bits in the Interrupt Enable Register determine whether or not an event will generate an interrupt. Interrupts can be masked globally by means of the INTENA bit of the DcMode Register (see Table 82). The active level and signalling mode of the INT output is controlled by the INTPOL and INTLVL bits of the DcHardwareConfiguration Register (see Table 84). Default settings after reset are active LOW and level mode. When pulse mode is selected, a pulse of 166 ns is generated when the OR-ed combination of all interrupt bits changes from logic 0 to logic 1. Bits RESET, RESUME, SP_EOT, EOT and SOF are cleared upon reading the DcInterrupt Register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated DcEndpointStatus Register. Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the current bus status when reading the DcInterrupt Register. SETUP and OUT token interrupts are generated after the DC has acknowledged the associated data packet. In bulk transfer mode, the DC will issue interrupts for every ACK received for an OUT token or transmitted for an IN token. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 20 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller In isochronous mode, an interrupt is issued upon each packet transaction. The firmware must take care of timing synchronization with the host. This can be done via the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the Interrupt Enable Register. If a Start-Of-Frame is lost, PSOF interrupts are generated every 1 ms. This allows the firmware to keep data transfer synchronized with the host. After 3 missed SOF events, the DC will enter `suspend' state. An alternative way of handling isochronous data transfer is to enable both the SOF and the PSOF interrupts and disable the interrupt for each isochronous endpoint. DC Interrupt register RESET SUSPND RESUME SOF EP14 . . . ... EP0IN EP0OUT EOT . . . . . . DC Device Mode register INTENA PULSE GENERATOR IERST IESUSP IERESM IESOF IEP14 . . . DC Hardware Configuration register INTLVL INTPOL 1 0 ... IEP0IN IEP0OUT IEEOT DC Interrupt Enable register INT2 MGT946 Fig 21. DC interrupt logic. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 21 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 9. USB host controller (HC) 9.1 HC's four USB states The ISP1161A USB HC has four USB states - USBOperational, USBReset, USBSuspend, and USBResume - that define the HC's USB signaling and bus states responsibilities. USBOperational USBReset write USBOperational write USBReset write USBOperational write USBResume USBReset USBSuspend write USBResume write or remote wake-up USBReset write USBSuspend MGT947 hardware or software reset Fig 22. ISP1161A HC USB states. The USB states are reflected in the HostControllerFunctionalState field of the HcControl Register (01H - read, 81H - write), which is located at bits 7 and 6 of the register. The Host Controller Driver (HCD) can perform only the USB state transitions shown in Figure 22. Remark: The Software Reset in Figure 22 is not caused by the HcSoftwareReset command. It is caused by the HostControllerReset field of the HcCommandStatus Register (02H - read, 82H - write). 9.2 Generating USB traffic USB traffic can be generated only when the ISP1161A USB HC is in the USBOperational state. Therefore, the HCD must set the HostControllerFunctionalState field of the HcControl Register before generating USB traffic. A simplistic flow diagram showing when and how to generate USB traffic is shown in Figure 23. For more detail, refer to the USB Specification Revision 2.0 about the protocol and ISP1161A USB HC register usage. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 22 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Reset Exit no Initialize HC HC state = USB_Operational Need USB traffic? yes Prepare PTD data in P system RAM Transfer PTD data into HC FIFO buffer RAM Entry HC informs HCD of USB traffic results HC performs USB transactions via USB bus I/F HC interprets PTD data MGT948 Fig 23. ISP1161A HC USB transaction loop * Reset This includes hardware reset by pin RESET and software reset by the HcSoftwareReset command (A9H). The reset function will clear all the HC's internal control registers to their reset status. After reset, the HCD must initialize the ISP1161A USB HC by setting some registers. * Initialize HC It includes: - Setting the physical size for the HC's internal FIFO buffer RAM by setting the HcITLBufferLength Register (2AH - read, AAH - write) and the HcATLBufferLength Register (2BH - read, ABH - write) - Setting the HcHardwareConfiguration Register according to requirements - Clearing interrupt events, if required - Enabling interrupt events, if required - Setting the HcFmInterval Register (0DH - read, 8DH - write) - Setting the HC's Root Hub registers - Setting the HcControl Register to move the HC into USBOperational state See also Section 9.5. * Entry The normal entry point. The microprocessor returns to this point when there are HC requests. * Need USB Traffic USB devices need the HC to generate USB traffic when they have USB traffic requests such as: - Connecting to or disconnecting from the downstream ports - Issuing the Resume signal to the HC To generate USB traffic, the HCD must enter the USB transaction loop. Prepare PTD data in P System RAM The communication between the HCD and the ISP1161A HC is in the form of Philips Transfer Descriptor (PTD) data. The PTD data provides USB traffic information about the commands, status, and USB data packets. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 23 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller The physical storage media of PTD data for the HCD is the microprocessor's system RAM. For the ISP1161A HC, the storage media is the internal FIFO buffer RAM. The HCD prepares PTD data in the microprocessor system RAM for transfer to the ISP1161A HC internal FIFO buffer RAM. * Transfer PTD data into HC's FIFO buffer RAM When PTD data is ready in the microprocessor's system RAM, the HCD must transfer the PTD data from the microprocessor's system RAM into the ISP1161A internal FIFO buffer RAM. * HC interprets PTD data The HC determines what USB transactions are required based on the PTD data that has been transferred into the internal FIFO buffer RAM. * HC performs USB transactions via USB Bus interface The HC performs the USB transactions with the specified USB device endpoint through the USB bus interface. * HC informs HCD the USB traffic results The USB transaction status and the feedback from the specified USB device endpoint will be put back into the ISP1161A HC internal FIFO buffer RAM in PTD data format. The HCD can read back the PTD data from the internal FIFO buffer RAM. 9.3 PTD data structure The Philips Transfer Descriptor (PTD) data structure provides communication between the HCD and the ISP1161A USB HC. The PTD data contains information required by the USB traffic. PTD data consists of a PTD followed by its payload data, as shown in Figure 24. FIFO buffer RAM top PTD PTD data #1 payload data PTD PTD data #2 payload data PTD payload data PTD data #N bottom MGT949 Fig 24. PTD data in FIFO buffer RAM. The PTD data structure is used by the HC to define a buffer of data that will be moved to or from an endpoint in the USB device. This data buffer is set up for the current frame (1 ms frame) by the HCD. The payload data for every transfer in the frame must have a PTD as a header to describe the characteristics of the transfer. PTD data is DWORD aligned. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 24 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 9.3.1 PTD data header definition The PTD forms the header of the PTD data. It tells the HC the transfer type, where the payload data goes, and the payload data's actual size. A PTD is an 8 byte data structure that is very important for HCD programming. Table 4: Bit Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Philips Transfer Descriptor (PTD): bit allocation 7 6 5 4 3 Active MaxPacketSize[7:0] EndpointNumber[3:0] reserved Format B5_5 reserved reserved Last TotalBytes[7:0] DirectionPID[1:0] TotalBytes[9:8] FunctionAddress[6:0] Speed MaxPacketSize[9:8] 2 Toggle 1 0 ActualBytes[7:0] CompletionCode[3:0] ActualBytes[9:8] 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 25 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 5: Symbol Philips Transfer Descriptor (PTD): bit description Access R/W R/W 0000 0001 0010 0011 0100 0101 0110 0111 1000 NoError CRC BitStuffing DataToggleMismatch Stall DeviceNotResponding PIDCheckFailure UnexpectedPID DataOverrun Description Contains the number of bytes that were transferred for this PTD General TD or isochronous data packet processing completed with no detected errors. Last data packet from endpoint contained a CRC error. Last data packet from endpoint contained a bit stuffing violation. Last packet from endpoint had data toggle PID that did not match the expected value. TD was moved to the Done queue because the endpoint returned a STALL PID. Device did not respond to token (IN) or did not provide a handshake (OUT). Check bits on PID from endpoint failed on data PID (IN) or handshake (OUT) Received PID was not valid when encountered or PID value is not defined. The amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in MaximumPacketSize field of ED) or the remaining buffer size. The endpoint returned is less than MaximumPacketSize and that amount was not sufficient to fill the specified buffer. During an IN, the HC received data from an endpoint faster than it could be written to system memory. During an OUT, the HC could not retrieve data from the system memory fast enough to keep up with the USB data rate. ActualBytes[9:0] CompletionCode[3:0] 1001 DataUnderrun 1010 1011 1100 1101 reserved reserved BufferOverrun BufferUnderrun Active R/W Set to logic 1 by firmware to enable the execution of transactions by the HC. When the transaction associated with this descriptor is completed, the HC sets this bit to logic 0, indicating that a transaction for this element will not be executed when it is next encountered in the schedule. Used to generate or compare the data PID value (DATA0 or DATA1). It is updated after each successful transmission or reception of a data packet. The maximum number of bytes that can be sent to or received from the endpoint in a single data packet. USB address of the endpoint within the function. Last PTD of a list (ITL or ATL). A logic 1 indicates that the PTD is the last PTD. Speed of the endpoint: 0 -- full speed 1 -- low speed Toggle MaxPacketSize[9:0] EndpointNumber[3:0] Last Speed R/W R R R R TotalBytes[9:0] R Specifies the total number of bytes to be transferred with this data structure. For Bulk and Control only, this can be greater than MaximumPacketSize. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09568 Product data Rev. 01 -- 02 August 2002 26 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 5: Symbol Philips Transfer Descriptor (PTD): bit description...continued Access R 00 01 10 11 SETUP OUT IN reserved Description DirectionPID[1:0] B5_5 R/W This bit is logic 0 at power-on reset. When this feature is not used, software used for ISP1161A is the same for ISP1160 and ISP1161. When this bit is set to logic 1 in this PTD for interrupt endpoint transfer, only 1 PTD USB transaction will be sent out in 1 ms. The format of this data structure. If this is a Control, Bulk or Interrupt endpoint, then Format = 0. If this is an Isochronous endpoint, then Format = 1. This is the USB address of the function containing the endpoint that this PTD refers to. Format FunctionAddress[6:0] R R 9.4 HC internal FIFO buffer RAM structure 9.4.1 Partitions According to the Universal Serial Bus Specification Rev. 2.0, there are four types of USB data transfers: Control, Bulk, Interrupt and Isochronous. The HC's internal FIFO buffer RAM has a physical size of 4 kbytes. This internal FIFO buffer RAM is used for transferring data between the microprocessor and USB peripheral devices. This on-chip buffer RAM can be partitioned into two areas: Acknowledged Transfer List (ATL) buffer and Isochronous (ISO)Transfer List (ITL) buffer. The ITL buffer is a Ping-Pong structured FIFO buffer RAM that is used to keep the payload data and their PTD header for Isochronous transfers. The ATL buffer is a non Ping-Pong structured FIFO buffer RAM that is used for the other three types of transfers. The ITL buffer can be further partitioned into ITL0 and ITL1 for the Ping-Pong structure. The ITL0 buffer and ITL1 buffer always have the same size. The microprocessor can put ISO data into either the ITL0 buffer or the ITL1 buffer. When the microprocessor accesses an ITL buffer, the HC can take over the other ITL buffer at the same time. This architecture improves the ISO transfer performance. The HCD can assign the logical size for the ATL buffer and ITL buffers at any time, but normally at initialization after power-on reset. This is done by setting the HcATLBufferLength Register (2BH - read, ABH - write) and HcITLBufferLength Register (2AH - read, AAH - write). The total buffer length cannot exceed the maximum RAM size of 4 kbytes (ATL buffer + ITL buffer). Figure 25 shows the partitions of the internal FIFO buffer RAM. When assigning buffer RAM sizes, follow this formula: ATL buffer length + 2 x (ITL buffer size) 1000H (that is, 4 kbytes) where: ITL buffer size = ITL0 buffer length = ITL1 buffer length The following assignments are examples of legal uses of the internal FIFO buffer RAM: * ATL buffer length = 800H, ITL buffer length = 400H. This is the maximum use of the internal FIFO buffer RAM. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 27 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller * ATL buffer length = 400H, ITL buffer length = 200H. This is insufficient use of the internal FIFO buffer RAM. * ATL buffer length = 1000H, ITL buffer length = 0H. This will use the internal FIFO buffer RAM for only ATL transfers. * ATL buffer length = 0H, ITL buffer length = 800H. This will use the internal FIFO buffer RAM for only ISO transfers. FIFO buffer RAM top ITL0 ITL buffer ITL1 ISO_B programmable sizes ISO_A ATL buffer ATL control/bulk/interrupt data not used bottom MGT950 4 kbytes Fig 25. HC internal FIFO buffer RAM partitions. The actual requirement for the buffer RAM need not reach the maximum size. You can make your selection based on your application. The following are some calculations of the ISO_A or ISO_B space for a frame of data: * Maximum number of useful data sent during one USB frame is 1280 bytes (20 ISO packets of 64 bytes). The total RAM size needed is: 20 x 8 + 1280 = 1440 bytes. * Maximum number of packets for different endpoints sent during one USB frame is 150 (150 ISO packets of 1 byte). The total RAM size needed is: 150 x 8 + 150 x 1 = 1350 bytes. * The Ping buffer RAM (ITL0) and the Pong buffer RAM (ITL1) have a maximum size of 2 kbytes each. All data needed for one frame can be stored in the Ping or the Pong buffer RAM. When the embedded system wants to initiate a transfer to the USB bus, the data needed for one frame is transferred to the ATL buffer or ITL buffer. The microprocessor detects the buffer status through the interrupt routines. When the HcBufferStatus Register (2CH - read only) indicates that the buffer is empty, then the microprocessor writes data into the buffer. When the HcBufferStatus Register indicates that the buffer is full, the data is ready on the buffer, and the microprocessor needs to read data from the buffer. During every 1 ms, there might be many events to generate interrupt requests to the microprocessor for data transfer or status retrieval. However, each of the interrupt types defined in this specification can be enabled or disabled by setting the HcPInterruptEnable Register bits accordingly. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 28 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller The data transfer can be done via the PIO mode or the DMA mode. The data transfer rate can go up to 15 Mbyte/s. In DMA operation, single-cycle or multi-cycle burst modes are supported. Multi-cycle burst modes of 1, 4, or 8 cycles per burst is supported for ISP1161A. 9.4.2 Data organization PTD data is used for every data transfer between a microprocessor and the USB bus, and the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the payload data is placed just after the PTD, after which the next PTD is placed. For an IN transfer, RAM space is reserved for receiving a number of bytes that is equal to the total bytes of the transfer. After this, the next PTD and its payload data are placed (see Figure 26). Remark: The PTD is defined for both ATL and ITL type data transfers. For ITL, the PTD data is put into ITL buffer RAM, and the ISP1161A takes care of the Ping-Pong action for the ITL buffer RAM access. RAM buffer top PTD of OUT transfer 000H payload data of OUT transfer PTD of IN transfer empty space for IN total data PTD of OUT transfer payload data of OUT transfer bottom MGT952 7FFH Fig 26. Buffer RAM data organization. The PTD data (PTD header and its payload data) is a structure of DWORD (doubleword or 4-byte) alignment. This means that the memory address is organized in blocks of 4 bytes. Therefore, the first byte of every PTD and the first byte of every payload data are located at an address which is a multiple of 4. Figure 27 illustrates an example in which the first payload data is 14 bytes long, meaning that the last byte of the payload data is at the location 15H. The next addresses (16H and 17H) are not multiples of 4. Therefore, the first byte of the next PTD will be located at the next multiple-of-four address, 18H. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 29 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller RAM buffer top PTD (8 bytes) 08H 00H payload data (14 bytes) 15H 18H PTD (8 bytes) 20H payload data MGT953 Fig 27. PTD data with DWORD alignment in buffer RAM. 9.4.3 Operation and C program example Figure 28 shows the block diagram for internal FIFO buffer RAM operations in PIO mode. The ISP1161A provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the access port is the ITLBufferPort Register (40H - read, C0H - write). For the ATL buffer RAM, the access port is the ATLBufferPort Register (41H - read, C1H - write). The buffer RAM is an array of bytes (8 bits) while the access port is a 16-bit register. Therefore, each read/write operation on the port accesses two consecutive memory locations, incrementing the pointer of the internal buffer RAM by two. The lower byte of the access port register corresponds to the data byte at the even location of the buffer RAM, and the upper byte corresponds to the next data byte at the odd location of the buffer RAM. Regardless of the number of data bytes to be transferred, the command code must be issued merely once, and it will be followed by a number of accesses of the data port (see Section 8.4). When the pointer of the buffer RAM reaches the value of the HcTransferCounter Register, an internal EOT signal will be generated to set bit 2, AllEOTInterrupt, of the HcPinterrupt Register and update the HcBufferStatus Register, to indicate that the whole data transfer has been completed. For ITL buffer RAM, every Start Of Frame (SOF) signal (1 ms) will cause toggling between ITL0 and ITL1, but this depends on the buffer status. If both ITL0BufferFull and ITL1BufferFull of the HcBufferStatus Register are already logic 1, meaning that both ITL0 and ITL1 buffer RAMs are full, the toggling will not happen. In this case, the microprocessor will always have access to ITL1. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 30 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 1 Host bus I/F command port Control registers data port 0 A0 22H/A2H 24H/A4H TransferCounter PInterrupt Commands Command register EOT 2 1 0 = 2CH 40H/C0H 41H/C1H BufferStatus ITLBufferPort ATLBufferPort (16-bit width) toggle T internal EOT SOF BufferStatus 000H 001H 000H 001H 000H 001H Pointer automatically increments by 2 3FFH ITL0 buffer RAM (8-bit width) 3FFH ITL1 buffer RAM (8-bit width) 7FFH ATL buffer RAM (8-bit width) MGT951 Fig 28. PIO access to internal FIFO buffer RAM. Following is an example of a C program that shows how to write data into the ATL buffer RAM. The total number of data bytes to be transferred is 80 (decimal) which will be set into the HcTransferCounter Register as 50H. The data consists of four types of PTD data: 1. The first PTD header (IN) is 8 bytes, followed by 16 bytes of space reserved for its payload data; 2. The second PTD header (IN) is also 8 bytes, followed by 8 bytes of space reserved for its payload data; 3. The third PTD header (OUT) is 8 bytes, followed by 16 bytes of payload data with values beginning from 0H to FH incrementing by 1; 4. The fourth PTD header (OUT) is also 8 bytes, followed by 8 bytes of payload data with values beginning from 0H to EH incrementing by 2. In all PTD's, we assign device address 5 and endpoint 1. ActualBytes is always zero (0). TotalBytes equals the number of payload data bytes. Table 6 shows the results after running this program. However, if communication with a peripheral USB device is desired, the device should be connected to the downstream port and pass enumeration. // The example program for writing ATL buffer RAM 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 31 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller #include Product data Rev. 01 -- 02 August 2002 32 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller outport(HcDataPort,PTDData[i]); }; // Check EOT interrupt bit wData = HcRegRead(wHcuPInterrupt); printf("\n HC Interrupt Status = %xH.\n",wData); // Check Buffer status register wData = HcRegRead(wHcBufferStatus); printf("\n HC Buffer Status = %xH.\n",wData); } // // Read HC 16-bit registers // unsigned int HcRegRead(unsigned int wIndex) { unsigned int wValue; outport(HcCmdPort,wIndex & 0x7f); wValue = inport(HcDataPort); return(wValue); } // // Write HC 16-bit registers // void HcRegWrite(unsigned int wIndex,unsigned int wValue) { outport(HcCmdPort,wIndex | 0x80); outport(HcDataPort,wValue); } Table 6: Run results of the C program example HC not initialized and not in HC initialized and in USBOperational state USBOperational state 0 1 1 0 No 1 1 1 1 Yes Comments Observed items HcPinterrupt Register Bit 1 (ATLInt) Bit 2 (AllEOTInterrupt) HcBufferStatus Register Bit 2 (ATLBufferFull) Bit 5 (ATLBufferDone) USB Traffic on USB Bus microprocessor must read ATL transfer completed transfer completed PTD data processed by HC OUT packets can be seen 9.5 HC operational model Upon power-up, the HCD initializes all operational registers (32-bit). The FSLargestDataPacket field (bits 30 to 16) of the HcFmInterval Register (0DH - read, 8DH - write) and the HcLSThreshold Register (11H - read, 91H - write) determine the end of the frame for full-speed and low-speed packets. By programming these fields, the effective USB bus usage can be changed. Furthermore, the size of the ITL buffers (HcITLBufferLength, 2AH - read, AAH - write) is programmed. In the case when a USB frame contains both ISO and AT packets, two interrupts will be generated per frame. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 33 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller One interrupt is issued concurrently with the SOF. This interrupt (the ITLint bit is set in the HcPInterrupt Register) triggers reading and writing of the ITL buffer by the microprocessor, after which the interrupt is cleared by the microprocessor. Next the programmable ATL Interrupt (the ATLint bit is set in the HcPInterrupt Register) is issued, which triggers reading and writing of the ATL buffer by the microprocessor, after which the interrupt is cleared by the microprocessor. If the microprocessor cannot handle the ISO interrupt before the next ISO interrupt, disrupted ISO traffic can result. To be able to send more than one packet to the same Control or Bulk endpoint in the same frame, an Active bit and a TotalBytes field are introduced (see Table 5). The Active bit is cleared only if all data of the Philips Transfer Descriptor (PTD) has been transferred or if a transaction at that endpoint contained a fatal error. If all PTDs of the ATL are serviced, and the frame is not over yet, the HC starts looking for a PTD with the Active bit still set. If such a PTD is found and there is still enough time in this frame, another transaction is started on the USB bus for this endpoint. For ISO processing, the HCD also has to take care of the HCBufferStatus Register (2CH, read only) for the ITL buffer RAM operations. After the HCD writes ISO data into ITL buffer RAM, the ITL0BufferFull or ITL1BufferFull bit (depends if it is ITL0 or ITL1) will be set to logic 1. After the HC processes the ISO data in the ITL buffer RAM, the corresponding ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1.The HCD can clear the buffer status bits by a read of the ITL buffer RAM. This must be done within the 1 ms frame from which the ITL0BufferDone or ITL1BufferDone was set. For example, the HCD writes ISO_A data into the ITL0 buffer in the first frame. This will cause the HCBufferStatus Register to show that the ITL0 buffer is full by setting the ITL0BufferFull bit to logic 1. At this stage the HCD cannot write ISO data into the ITL0 buffer RAM again. In the second frame, the HC will process the ISO-A data in the ITL0 buffer. At the same time, the HCD can write ISO-B data into ITL1 buffer. When the next SOF comes (the beginning of the third frame), both the ITL1BufferFull and ITL0BufferDone are automatically set to logic 1. In the third frame the HCD has to read at least two bytes (one word) of the ITL0 buffer to clear both the ITL0BufferFull and ITL0BufferDone bits. If both are not cleared, when the next SOF comes (the beginning of the fourth frame) the ITL0BufferDone and ITL0BufferFull bits will be cleared automatically. This also applies to the ITL1 buffer because the ITL0 and ITL1 are Ping-Pong structured buffers. To recover from this state, a power-on reset or software reset will have to be applied. 9.5.1 Time domain behavior In example 1 (Figure 29), the microprocessor is fast enough to read back and download a scenario before the next interrupt. Note that on the ISO interrupt of frame N: * The ISO packet for frame N + 1 will be written * The AT packet for frame N + 1 will be written. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 34 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller AT interrupt SOF (frame N) traffic on USB (frame N + 1) (frame N + 2) (frame N + 3) MGT954 ISO interrupt read ISO_A(N - 1) write ISO_A(N + 1) read AT(N) write AT(N + 1) Fig 29. HC time domain behavior: example 1. In example 2 (Figure 30), the microprocessor is still busy transferring the AT data when the ISO interrupt of the next frame (N + 1) is raised. As a result, there will be no AT traffic in frame N + 1. The HC does not raise an AT interrupt in frame N + 1. The AT part is simply postponed until frame N + 2. On the AT N + 2 interrupt, the transfer mechanism is back to normal operation. This simple mechanism ensures, among other things, that Control transfers are not dropped systematically from the USB in case of an overloaded microprocessor. (frame N) (frame N + 1) (frame N + 2) (frame N + 3) MGT955 Fig 30. HC time domain behavior: example 2. In example 3 (Figure 31), the ISO part is still being written while the Start of Frame (SOF) of the next frame has occurred. This will result in undefined behavior for the ISO data on the USB bus in frame N + 1 (depending on if the exact timing data is corrupted or not). The HC should not raise an AT interrupt in frame N + 1. (frame N) (frame N + 1) (frame N + 2) (frame N + 3) MGT956 Fig 31. HC time domain behavior: example 3. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 35 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 9.5.2 Control transaction limitations The different phases of a Control transfer (SETUP, Data and Status) should never be put in the same ATL. 9.6 Microprocessor loading The maximum amount of data that can be transferred for an endpoint during one frame is 1023 bytes. The number of USB packets that are needed for this batch of data depends on the maximum packet size that is specified. The HCD has to schedule the transactions in a frame. On the other hand, the HCD must have the ability to handle the interrupts coming from the HC every 1 ms. It must also be able to do the scheduling for the next frame, reading the frame information from and writing the next frame information to the buffer RAM in the time between the end of the current frame and the start of the next frame. 9.7 Internal pull-down resistors for downstream ports There are four internal 15 k pull-down resistors built into the ISP1161A for the two downstream ports: two resistors for each port. These resistors are software selectable by programming bit 12 (2_DownstreamPort15K resistorsel) of the HcHardwareConfiguration Register (20H - read, A0H - write). When bit 12 is logic 0, external 15 k pull-down resistors are used. If bit 12 is set to logic 1, the internal 15 k pull-down resistors are used. See Figure 32. This feature is a cost-saving option. However, the power-on reset default value of bit 12 is logic 0. If using the internal resistors, the HCD must set this bit status after every reset, because a reset action (hardware or software) will clear this bit. VBUS USB connector ISP1161A D- D+ 22 HcHardware Configuration bit 12 47 pF (2x) 22 internal 15 k (2x) external 15 k (2x) 004aaa088 Using either internal or external 15 k resistors. Fig 32. Use of 15 k pull-down resistors on downstream ports. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 36 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 9.8 OC detection and power switching control A downstream port provides +5 V power supply to VBUS. The ISP1161A has built-in hardware functions to monitor the downstream ports loading conditions and control their power switching. These hardware functions are implemented by the internal power switching control circuit and overcurrent detection circuit. H_PSW1 and H_PSW2 are power switching control output pins (active LOW, open drain) for downstream port 1 and 2, respectively. H_OC1 and H_OC2 are overcurrent detection input pins for downstream ports 1 and 2, respectively. Figure 33 shows the ISP1161A downstream port power management scheme (`n' represents the downstream port numbers, n = 1 or 2). regulator V CC (+5 V or +3.3 V) OC detect HC CORE HcHardware Configuration bit 10 OC select 1 0 Reg PSW H_OCn H_PSWn C/L ISP1161A 004aaa089 `n' represents the downstream port number (n = 1 or 2) Fig 33. Downstream port power management scheme. 9.8.1 Using an internal OC detection circuit The internal OC detection circuit can be used only when VCC (pin 56) is connected to a +5 V power supply. The HCD must set AnalogOCEnable, bit 10 of the HcHardwareConfiguration Register, to logic 1. An application using the internal OC detection circuit and internal 15 k pull-down resistors is shown in Figure 34. In this example, the HCD must set both AnalogOCEnable and DownstreamPort15KresistorSel to logic 1. They are bit 10 and bit 12 of the HcHardwareConfiguration Register, respectively. When H_OCn detects an overcurrent status on a downstream port, H_PSWn will output HIGH, a logic 1 to turn off the +5 V power supply to the downstream port VBUS. When there is no such condition, H_PSWn will output LOW, a logic 0 to turn on the +5 V power supply to the downstream port VBUS. In general applications, a P-channel MOSFET can be used as the power switch for VBUS. Connect the +5 V power supply to the drain of the P-channel MOSFET, VBUS to the source, and H_PSWn to the gate. Call the voltage drop across the drain and source the overcurrent detection voltage (VOC). For the internal overcurrent detection circuit, a voltage comparator has been incorporated with a nominal voltage threshold 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 37 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller (Vtrip) of 75 mV. When VOC exceeds Vtrip, H_PSWn will output a HIGH level, logic 1 to turn off the P-channel MOSFET. If the P-channel MOSFET has a RDSon of 150 m, the overcurrent threshold will be 500 mA. The selection of a P-channel MOSFET with a different RDSon will result in a different overcurrent threshold. regulator P-Ch MOSFET +5 V VCC OC detect HC CORE HcHardware Configuration bit 10 OC select 1 0 Reg V = + 5 V - VBUS H_OCn VBUS H_PSWn USB downstream port connector 22 22 PSW C/L H_DMn ATX H_DPn 47 pF (2x) bit 12 SIE HcHardware Configuration 15 k (2x) ISP1161A 004aaa090 `n' represents the downstream port number (n = 1 or 2) Fig 34. Using internal OC detection circuit. 9.8.2 Using an external OC detection circuit When VCC (pin 56) is connected to a +3.3 V instead of the +5 V power supply, the internal OC detection circuit cannot be used. An external OC detection circuit must be used instead. Regardless of the VCC value, an external OC detection circuit can always be used. To use an external OC detection circuit, AnalogOCEnable, bit 10 of the HcHardwareConfiguration Register, must be logic 0. By default after reset, this bit is already logic 0; therefore, the HCD does not need to clear this bit. Figure 35 shows how to use an external OC detection circuit. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 38 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller + 3.3 V or + 5 V regulator VCC VBUS external OC detect Vo Vi OC EN H_PSWn USB downstream port connector 22 22 C/L H_OCn +5 V OC detect HC CORE HcHardware Configuration bit 10 OC select 1 0 Reg PSW H_DMn ATX H_DPn 47 pF (2x) bit 12 SIE HcHardware Configuration 15 k (2x) ISP1161A 004aaa091 `n' represents the downstream port number (n = 1 or 2) Fig 35. Using an external OC detection circuit. 9.9 Suspend and wake-up 9.9.1 HC suspended state The HC can be put into suspended state by setting the HcControl Register (01H read, 81H - write). See Figure 22 for the HC's flow of USB state changes. XOSC_6MHz XOSC On (to DC PLL) On PLL_Lock HC PLL PLL_ClkOut HC_ClkOk DIGITAL CLOCK SWITCH On HC_Clk48MOut HC_RawClk48M HC_EnableClock HC CORE HcHardware Configuration On VOLTAGE REGULATOR H_Wakeup (pin) DC_EnableClock bit 11 (SuspendClkNotStop) HC_NeedClock CS (pin) MGT958 Fig 36. ISP1161A suspend and resume clock scheme. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 39 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller In suspended state, the device will consume considerably less power by turning off the internal 48 MHz clock, PLL and crystal, and setting the internal regulator to power-down mode. The ISP1161A suspend and resume clock scheme is shown in Figure 36. Remark: The ISP1161A can only be put into a fully suspended state only after both the HC and the DC go into suspend state. At this point, the crystal can be turned off and the internal regulator can be put into power-down mode. Pin H_SUSPEND is the sensing output pin for HC's suspended state. When the HC goes into USBSuspend state, this pin will output a HIGH level (logic 1). This pin is cleared to LOW (logic 0) level only when the HC is put into a USBReset state or USBOperational state (refer to the HcControl Register bits 7 to 6, 01H - read, 81H write). Bit 11, SuspendClkNotStop, of the HcHardwareConfiguration Register (20H read, A0H - write), defines if the HC internal clock is stopped or kept running when the HC goes into USBSuspend state. After the HC enters the USBSuspend state for 1.3 ms, the internal clock will be stopped if bit SuspendClkNotStop is logic 0. 9.9.2 HC wake-up from suspended state There are three methods to wake up the HC from the USBSuspend state: hardware wake-up, software wake-up, and USB bus resume. They are described as follows: Wake-up by pin H_WAKEUP: Pins H_SUSPEND and H_WAKEUP provide a method of remote wake-up control for the HC without the need to access the HC internal registers. H_WAKEUP is an external wake-up control input pin for the HC. After the HC goes into USBSuspend state, it can be woken up by sending a HIGH level pulse to pin H_WAKEUP. This will turn on the HC's internal clock, and set bit 6, ClkReady, of the HcPInterrupt Register (24H - read, A4H - write). Under the USBSuspend state, once pin H_WAKEUP goes HIGH, after 160 s, the internal clock will be up. If pin H_WAKEUP continues to be HIGH, then the internal clock will be kept running, and the microprocessor can set the HC into USBOperational state during this time. If H_WAKEUP goes LOW for more than 1.14 ms, the internal clock stops, and the HC goes back into USBSuspend state. Wake-up by pin CS (software wake-up): During the USBSuspend state, an external microprocessor issues a chip select signal through pin CS. This method of access to ISP1161A internal registers is a software wake-up. Wake-up by USB devices: For a USB bus resume, a USB device attached to the root hub port issues a resume signal to the HC through the USB bus, switching the HC from USBSuspend state to USBResume state. This will also set the ResumeDetected bit of the HcInterruptStatus Register (03H - read, 83H - write). No matter which method is used to wake up the HC from USBSuspend state, the corresponding interrupt bits must be enabled before the HC goes into USBSuspend state so that the microprocessor can receive the correct interrupt request to wake up the HC. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 40 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10. HC registers The HC contains a set of on-chip control registers. These registers can be read or written by the Host Controller Driver (HCD). The Control and Status register sets, Frame Counter register sets, and Root Hub register sets are grouped under the category of HC Operational registers (32 bits). These operational registers are made compatible to OpenHCI (Host Controller Interface) Operational registers. This allows the OpenHCI HCD to be easily ported to ISP1161A. Reserved bits may be defined in future releases of this specification. To ensure interoperability, the HCD must not assume that a reserved field contains logic 0. Furthermore, the HCD must always preserve the values of the reserved field. When a R/W register is modified, the HCD must first read the register, modify the bits desired, and then write the register with the reserved bits still containing the original value. Alternatively, the HCD can maintain an in-memory copy of previously written values that can be modified and then written to the HC register. When a `write to set' or `clear the register' is performed, bits written to reserved fields must be logic 0. As shown in Table 7, the addresses (the commands for accessing registers) of these 32-bit Operational Registers are similar the offsets defined in the OHCI specification with the addresses being equal to offset DIV 4: Table 7: read 00 01 02 03 04 05 0D 0E 0F 11 12 13 14 15 16 20 21 22 24 25 HC Control Register summary Register HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcFmInterval HcFmRemaining HcFmNumber HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus[1] HcRhPortStatus[2] HcHardwareConfiguration HcDMAConfiguration HcTransferCounter HcPInterrupt HcPInterruptEnable Width Reference 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 16 Section 10.1.1 on page 42 Section 10.1.2 on page 43 Section 10.1.3 on page 44 Section 10.1.4 on page 45 Section 10.1.5 on page 46 Section 10.1.6 on page 48 Section 10.2.1 on page 49 Section 10.2.2 on page 50 Section 10.2.3 on page 51 Section 10.2.4 on page 52 Section 10.3.1 on page 53 Section 10.3.2 on page 55 Section 10.3.3 on page 56 Section 10.3.4 on page 58 Section 10.3.4 on page 58 Section 10.4.1 on page 62 Section 10.4.2 on page 63 Section 10.4.3 on page 64 Section 10.4.4 on page 65 Section 10.4.5 on page 66 HC DMA and Interrupt Control Registers HC Root Hub Registers HC Frame Counter Registers Functionality HC Control and Status Registers write 81 82 83 84 85 8D 91 92 93 94 95 96 A0 A1 A2 A4 A5 Command (Hex) 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 41 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 7: read 27 28 2A 2B 2C 2D 2E 40 41 HC Control Register summary...continued Register HcChipID HcScratch HcSoftwareReset HcITLBufferLength HcATLBufferLength HcBufferStatus HcReadBackITL0Length HcReadBackITL1Length HcITLBufferPort HcATLBufferPort Width Reference 16 16 16 16 16 16 16 16 16 16 Section 10.5.1 on page 67 Section 10.5.2 on page 68 Section 10.5.3 on page 68 Section 10.6.1 on page 69 Section 10.6.2 on page 69 Section 10.6.3 on page 70 Section 10.6.4 on page 71 Section 10.6.5 on page 71 Section 10.6.6 on page 72 Section 10.6.7 on page 72 HC Buffer RAM Control Registers Functionality HC Miscellaneous Registers write A8 A9 AA AB C0 C1 Command (Hex) 10.1 HC control and status registers 10.1.1 HcRevision Register (R: 00H) Code (Hex): 00 -- read only Table 8: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Table 9: Bit 31 to 8 7 to 0 7 6 5 4 REV[7:0] 10H R HcRevision Register: bit description Symbol - REV[7:0] Description Reserved Revision: This read-only field contains the BCD representation of the version of the HCI specification that is implemented by this HC. For example, a value of 11H corresponds to version 1.1. All HC implementations that are compliant with this specification will have a value of 10H. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. HcRevision Register: bit allocation 31 30 29 28 reserved 00H R 23 22 21 20 reserved 00H R 15 14 13 12 reserved 00H R 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 9397 750 09568 Product data Rev. 01 -- 02 August 2002 42 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10.1.2 HcControl Register (R/W: 01H/81H) The HcControl Register defines the operating modes for the HC. RemoteWakeupEnable (RWE) is modified only by the HCD. Code (Hex): 01 -- read Code (Hex): 81 -- write Table 10: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcControl Register: bit allocation 31 30 29 28 reserved 00H R/W 23 22 21 20 reserved 00H R/W 15 0 R/W 7 HCFS[1:0] 0 R/W 0 R/W Table 11: Bit 31 to 11 10 0 R/W 0 R/W 0 R/W 14 0 R/W 6 13 reserved 0 R/W 5 0 R/W 4 0 R/W 3 reserved 0 R/W 0 R/W 0 R/W 12 11 10 RWE 0 R/W 2 9 RWC 0 R/W 1 8 reserved 0 R/W 0 19 18 17 16 27 26 25 24 HcControl Register: bit description Symbol RWE Description reserved RemoteWakeupEnable: This bit is used by the HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. When this bit is set and the ResumeDetected bit in HcInterruptStatus is set, a remote wake-up is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt. RemoteWakeupConnected: This bit indicates whether the HC supports remote wake-up signaling. If remote wake-up is supported and used by the system, it is the responsibility of system firmware to set this bit during POST. The HC clears the bit upon a hardware reset but does not alter it upon a software reset. Remote wake-up signaling of the host system is host-bus-specific, and is not described in this specification. 9 RWC 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 43 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcControl Register: bit description...continued Symbol HCFS Description reserved HostControllerFunctionalState for USB: 00B -- USBReset 01B -- USBResume 10B -- USBOperational 11B -- USBSuspend A transition to USBOperational from another state causes start-of-frame (SOF) generation to begin 1 ms later. The HCD determines whether the HC has begun sending SOFs by reading the StartofFrame field of HcInterruptStatus. This field can be changed by the HC only when in the USBSuspend state. The HC can move from the USBSuspend state to the USBResume state after detecting the resume signaling from a downstream port. The HC enters USBReset after a software reset and a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. Table 11: Bit 8 7 to 6 5 to 0 - reserved 10.1.3 HcCommandStatus Register (R/W: 02H/82H) The HcCommandStatus Register is used by the HC to receive commands issued by the HCD, and it also reflects the HC's current status. To the HCD, it appears to be a `write to set' register. The HC must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. The HCD may issue multiple distinct commands to the HC without concern for corrupting previously issued commands. The HCD has normal read access to all bits. The SchedulingOverrunCount field indicates the number of frames with which the HC has detected the scheduling overrun error. This occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the HC increments the counter and sets the SchedulingOverrun field in the HcInterruptStatus Register. Code (Hex): 02 -- read Code (Hex): 82 -- write Table 12: Bit Symbol Reset Access Bit Symbol Reset Access HcCommandStatus Register: bit allocation 31 30 29 28 reserved 00H R 23 0 R 22 0 R 21 reserved 0 R 0 R 0 R 0 R 0 R 20 19 18 17 SOC[1:0] 0 R 16 27 26 25 24 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 44 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 13 12 reserved 00H R/W 11 10 9 8 Bit Symbol Reset Access Bit Symbol Reset Access 15 14 7 0 R/W 6 0 R/W Table 13: Bit 31 to 18 17 to 16 5 0 R/W 4 reserved 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 HCR 0 R/W HcCommandStatus Register: bit description Symbol SOC[1:0] Description reserved SchedulingOverrunCount: The field is incremented on each scheduling overrun error. It is initialized to 00B and wraps around at 11B. It will be incremented when a scheduling overrun is detected even if SchedulingOverrun in HcInterruptStatus has already been set. This is used by HCD to monitor any persistent scheduling problems. reserved HostControllerReset: This bit is set by the HCD to initiate a software reset of the HC. Regardless of the functional state of HC, it moves to the USBSuspend state in which most of the operational registers are reset, except those stated otherwise, and no Host bus accesses are allowed. This bit is cleared by HC upon the completion of the reset operation. The reset operation must be completed within 10 s. This bit, when set, does not cause a reset to the Root Hub and no subsequent reset signaling will be asserted to its downstream ports. 15 to 1 0 HCR 10.1.4 HcInterruptStatus Register (R/W: 03H/83H) This register provides the status of the events that cause hardware interrupts. When an event occurs, the HC sets the corresponding bit in this register. When a bit is set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable Register (see Section 10.1.5) and the MasterInterruptEnable bit is set. The HCD can clear individual bits in this register by writing logic 1 to the bit positions to be cleared, but cannot set any of these bits. Conversely, The HC can set bits in this register, but cannot clear the bits. Code (Hex): 03 -- read Code (Hex): 83 -- write Table 14: Bit Symbol Reset Access HcInteruptStatus Register: bit allocation 31 30 29 28 reserved 00H R/W 27 26 25 24 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 45 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 21 20 reserved 00H R/W 19 18 17 16 Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 23 22 15 14 13 12 reserved 00H R/W 11 10 9 8 7 reserved 0 R/W 6 RHSC 0 R/W Table 15: Bit 31 to 7 6 5 FNO 0 R/W 4 UE 0 R/W 3 RD 0 R/W 2 SF 0 R/W 1 reserved 0 R/W 0 SO 0 R/W HcInterruptStatus Register: bit description Symbol RHSC Description reserved RootHubStatusChange: This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[1:2] has changed. FrameNumberOverflow: This bit is set when the MSB of HcFmNumber (bit 15) changes value. UnrecoverableError: This bit is set when the HC detects a system error not related to USB. The HC does not proceed with any processing nor signaling before the system error has been corrected. The HCD clears this bit after the HC has been reset. OHCI: Always set to logic 0. ResumeDetected: This bit is set when the HC detects that a device on the USB is asserting resume signaling from a state of no resume signaling. This bit is not set when HCD enters the USBResume state. StartofFrame: At the start of each frame, this bit is set by the HC and an SOF is generated. reserved SchedulingOverrun: This bit is set when the USB schedules for current frame overruns. A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be incremented. 5 4 FNO UE 3 RD 2 1 0 SF SO 10.1.5 HcInterruptEnable Register (R/W: 04H/84H) Each enable bit in the HcInterruptEnable Register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable Register is used to control which events generate a hardware interrupt. A hardware interrupt is requested on the host bus when three conditions occur: * A bit is set in the HcInterruptStatus Register * The corresponding bit in the HcInterruptEnable Register is set * The MasterInterruptEnable bit is set. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 46 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Writing a logic 1 to a bit in this register sets the corresponding bit, whereas writing a logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the current value of this register is returned. Code (Hex): 04 -- read Code (Hex): 84 -- write Table 16: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 7 reserved 0 R/W 6 RHSC 0 R/W Table 17: Bit 31 5 FNO 0 R/W 4 UE 0 R/W 15 14 13 12 reserved 00H R/W 3 RD 0 R/W 2 SF 0 R/W 1 reserved 0 R/W 0 SO 0 R/W HcInterruptEnable Register: bit allocation 31 MIE 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 reserved 00H R/W 11 10 9 8 30 29 28 27 reserved 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 26 25 24 HcInterruptEnable Register: bit description Symbol MIE Description MasterInterruptEnable by the HCD: A logic 0 is ignored by the HC. A logic 1 enables interrupt generation by events specified in other bits of this register. reserved 0 -- ignore 1 -- enable interrupt generation due to Root Hub Status Change 0 -- ignore 1 -- enable interrupt generation due to Frame Number Overflow 0 -- ignore 1 -- enable interrupt generation due to Unrecoverable Error 0 -- ignore 1 -- enable interrupt generation due to Resume Detect 0 -- ignore 1 -- enable interrupt generation due to Start of Frame reserved 0 -- ignore 1 -- enable interrupt generation due to Scheduling Overrun 30 to 7 6 5 4 3 2 1 0 RHSC FNO UE RD SF SO 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 47 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10.1.6 HcInterruptDisable Register (R/W: 05H/85H) Each disable bit in the HcInterruptDisable Register corresponds to an associated interrupt bit in the HcInterruptStatus Register. The HcInterruptDisable Register is coupled with the HcInterruptEnable Register. Thus, writing a logic 1 to a bit in this register clears the corresponding bit in the HcInterruptEnable Register, whereas writing a logic 0 to a bit in this register leaves the corresponding bit in the HcInterruptEnable Register unchanged. On a read, the current value of the HcInterruptEnable Register is returned. Code (Hex): 05 -- read Code (Hex): 85 -- write Table 18: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcInterruptDisable Register: bit allocation 31 MIE 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 reserved 00H R/W 15 14 13 12 reserved 00H R/W 7 reserved 0 R/W 6 RHSC 0 R/W Table 19: Bit 31 5 FNO 0 R/W 4 UE 0 R/W 3 RD 0 R/W 2 SF 0 R/W 1 reserved 0 R/W 0 SO 0 R/W 11 10 9 8 30 29 28 27 reserved 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 26 25 24 HcInterruptDisable Register: bit description Symbol MIE Description A logic 0 is ignored by the HC. A logic 1 disables interrupt generation due to events specified in other bits of this register. This bit is set after a hardware or software reset. reserved 0 -- ignore 1 -- disable interrupt generation due to Root Hub Status Change 0 -- ignore 1 -- disable interrupt generation due to Frame Number Overflow 30 to 7 6 5 RHSC FNO 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 48 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcInterruptDisable Register: bit description...continued Symbol UE RD SF SO Description 0 -- ignore 1 -- disable interrupt generation due to Unrecoverable Error 0 -- ignore 1 -- disable interrupt generation due to Resume Detect 0 -- ignore 1 -- disable interrupt generation due to Start of Frame reserved 0 -- ignore 1 -- disable interrupt generation due to Scheduling Overrun Table 19: Bit 4 3 2 1 0 10.2 HC frame counter registers 10.2.1 HcFmInterval Register (R/W: 0DH/8DH) The HcFmInterval Register contains a 14-bit value which indicates the bit time interval in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the full-speed maximum packet size that the HC may transmit or receive without causing a scheduling overrun. The HCD may carry out minor adjustments on the FrameInterval by writing a new value at each SOF. This allows the HC to synchronize with an external clock source and to adjust any unknown clock offset. Code (Hex): 0D -- read Code (Hex): 8D -- write Table 20: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 7 15 reserved 0 R/W 6 1 R/W 5 0 R/W 4 FI[7:0] DFH R/W 1 R/W 3 14 13 12 HcFmInterval Register: bit allocation 31 FIT 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 00H R/W 11 FI[13:8] 1 R/W 2 1 R/W 1 0 R/W 0 10 9 8 30 29 28 27 FSMPS[14:8] 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 26 25 24 FSMPS[7:0] 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 49 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcFmInterval Register: bit description Symbol FIT FSMPS [14:0] Description FrameIntervalToggle: The HCD toggles this bit whenever it loads a new value to FrameInterval. FSLargestDataPacket (FSMaximumPacketSize): Specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. The counter value represents the largest amount of data in bits which can be sent or received by the HC in a single transaction at any given time without causing a scheduling overrun. The field value is calculated by the HCD. reserved FrameInterval: Specifies the interval between two consecutive SOFs in bit times. The default value is 11999. The HCD must save the current value of this field before resetting the HC. Setting the HostControllerReset of the HcCommandStatus Register will cause the HC to reset this field to its default value. HCD may choose to restore the saved value upon completing the Reset sequence. Table 21: Bit 31 30 to 16 15 to 14 13 to 0 FI[13:0] 10.2.2 HcFmRemaining Register (R: 0EH) The HcFmRemaining Register is a 14-bit down counter showing the bit time remaining in the current frame. Code (Hex): 0E -- read Table 22: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcFmRemaining Register: bit allocation 31 FRT 0 R 23 0 R 22 0 R 21 0 R 20 reserved 00H R 15 reserved 0 R 7 0 R 6 0 R 5 0 R 4 FR[7:0] 00H R 0 R 3 14 13 12 11 FR[13:8] 0 R 2 0 R 1 0 R 0 10 9 8 30 29 28 27 reserved 0 R 19 0 R 18 0 R 17 0 R 16 26 25 24 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 50 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcFmRemaining Register: bit description Symbol FRT Description FrameRemainingToggle: This bit is loaded from the FrameIntervalToggle field of the HcFmInterval register whenever FrameRemaining reaches 0. This bit is used by the HCD for synchronization between FrameInterval and FrameRemaining. reserved FrameRemaining: This counter is decremented at each bit time. When it reaches zero, it is reset by loading the FrameInterval value specified in the HcFmInterval register at the next bit time boundary. When entering the USBOperational state, the HC reloads it with the content of the FrameInterval part of the HcFmInterval Register and uses the updated value from the next SOF. Table 23: Bit 31 30 to 14 13 to 0 FR[13:0] 10.2.3 HcFmNumber Register (R: 0FH) The HcFmNumber Register is a 16-bit counter. It provides a timing reference for events happening in the HC and the HCD. The HCD may use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to the register. Code (Hex): 0F -- read Table 24: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HCFmNumber Register: bit allocation 31 30 29 28 reserved 00H R 23 22 21 20 reserved 00H R 15 14 13 12 FN[15:8] 00H R 7 6 5 4 FN[7:0] 00H R Table 25: Bit 31 to 16 15 to 0 HcFmNumber Register: bit description Symbol - FN[15:0] Description reserved FrameNumber: This field is incremented when HcFmRemaining is reloaded. It rolls over to 0000H after FFFFH. When the USBOperational state is entered, this field will be incremented automatically. HC will set the StartofFrame bit in the HcInterruptStatus Register. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 9397 750 09568 Product data Rev. 01 -- 02 August 2002 51 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10.2.4 HcLSThreshold Register (R/W: 11H/91H) The HcLSThreshold Register contains an 11-bit value used by the HC to determine whether to commit to the transfer of a maximum of 8-byte LS packet before EOF. Neither the HC nor the HCD is allowed to change this value. Code (Hex): 11 -- read Code (Hex): 91 -- write Table 26: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcLSThreshold Register: bit allocation 31 30 29 28 reserved 00H R/W 23 22 21 20 reserved 00H R/W 15 0 R/W 7 14 0 R/W 6 13 reserved 0 R/W 5 0 R/W 4 LST[7:0] 28H R/W Table 27: Bit 31 to 11 10 to 0 HcLSThreshold Register: bit description Symbol - LST[10:0] Description reserved LSThreshold: Contains a value that is compared to the FrameRemaining field before a low-speed transaction is initiated. The transaction is started only if FrameRemaining this field. The value is calculated by the HCD, which considers transmission and set-up overhead.Default value: 1576 (628H) 0 R/W 3 1 R/W 2 12 11 10 9 LST[10:8] 1 R/W 1 0 R/W 0 8 19 18 17 16 27 26 25 24 10.3 HC Root Hub Registers All registers included in this partition are dedicated to the USB Root Hub, which is an integral part of the HC although it is functionally a separate entity. The Host Controller Driver (HCD) emulates USBD accesses to the Root Hub via a register interface. The HCD maintains many USB-defined hub features that are not required to be supported in hardware. For example, the Hub's Device, Configuration, Interface, Endpoint Descriptors, as well as some static fields of the Class Descriptor, are maintained only in the HCD. The HCD also maintains and decodes the Root Hub's device address as well as other minor operations more suited for software than for hardware. The Root Hub registers were developed to match the bit organization and operation of typical hubs found in the system. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 52 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Four 32-bit registers have been defined: * * * * HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus[1:NDP] Each register is read and written as a DWORD. These registers are only written during initialization to correspond with the system implementation. The HcRhDescriptorA and HcRhDescriptorB registers are writeable regardless of the HCs USB states. HcRhStatus and HcRhPortStatus are writeable during the USBOperational state only. 10.3.1 HcRhDescriptorA Register (R/W: 12H/92H) The HcRhDescriptorA Register is the first register of two describing the characteristics of the Root Hub. Reset values are Implementation-Specific (IS). The descriptor length (11), descriptor type and hub controller current (0) fields of the hub Class Descriptor are emulated by the HCD. All other fields are located in the registers HcRhDescriptorA and HcRhDescriptorB. Remark: IS denotes an implementation-specific reset value for that field. Code (Hex): 12 -- read Code (Hex): 92 -- write Table 28: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R 0 R 0 R 7 15 14 reserved 0 R 6 0 R 5 reserved 0 R 0 R 0 R IS R 13 12 NOCP IS R/W 4 23 22 21 20 reserved 00H R/W 11 OCPM IS R/W 3 10 DT 0 R 2 9 NPS IS R/W 1 NDP[1:0] IS R 8 PSM IS R/W 0 HcRhDescriptorA Register: bit description 31 30 29 28 IS R/W 19 18 17 16 27 26 25 24 POTPGT[7:0] 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 53 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcRhDescriptorA Register: bit description Symbol POTPGT [7:0] Description PowerOnToPowerGoodTime: This byte specifies the duration HCD has to wait before accessing a powered-on port of the Root Hub. The unit of time is 2 ms. The duration is calculated as POTPGT x 2 ms. reserved NoOverCurrentProtection: This bit describes how the overcurrent status for the Root Hub ports are reported. When this bit is cleared, the OverCurrentProtectionMode field specifies global or per-port reporting. 0 -- overcurrent status is reported collectively for all downstream ports 1 -- no overcurrent reporting supported Table 29: Bit 31 to 24 23 to 13 12 NOCP 11 OCPM OverCurrentProtectionMode: This bit describes how the overcurrent status for the Root Hub ports is reported. At reset, this field reflects the same mode as PowerSwitchingMode. This field is valid only if the NoOverCurrentProtection field is cleared. 0 -- overcurrent status is reported collectively for all downstream ports. 1 -- overcurrent status is reported on a per-port basis. On power-up, clear this bit and then set it to logic 1. 10 DT DeviceType: This bit specifies that the Root Hub is not a compound device--it is not permitted. This field will always read/write 0. NoPowerSwitching: These bits are used to specify whether power switching is supported or ports are always powered. It is implementation-specific. When this bit is cleared, the bit PowerSwitchingMode specifies global or per-port switching. 0 -- ports are power switched 1 -- ports are always powered on when the HC is powered on 9 NPS 8 PSM PowerSwitchingMode: This bit is used to specify how the power switching of the Root Hub ports is controlled. It is implementation-specific. This field is valid only if the NoPowerSwitching field is cleared. 0 -- all ports are powered at the same time 1 -- each port is powered individually. This mode allows port power to be controlled by either the global switch or per-port switching. If the bit PortPowerControlMask is set, the port responds to only port power commands (Set/ClearPortPower). If the port mask is cleared, then the port is controlled only by the global power switch (Set/ClearGlobalPower). 7 to 2 1 to 0 NDP[1:0] reserved NumberDownstreamPorts: These bits specify the number of downstream ports supported by the Root Hub. The maximum number of ports supported by ISP1161A is 2. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 54 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10.3.2 HcRhDescriptorB Register (R/W: 13H/93H) The HcRhDescriptorB Register is the second register of two describing the characteristics of the Root Hub. These fields are written during initialization to correspond with the system implementation. Reset values are implementation-specific (IS). Code (Hex): 13 -- read Code (Hex): 93 -- write Table 30: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcRhDescriptorB Register: bit allocation 31 30 29 28 reserved N/A R 23 N/A R 15 22 N/A R 14 21 reserved N/A R 13 N/A R 12 reserved N/A R 7 N/A R 6 N/A R Table 31: Bit 31 to 19 18 to 16 5 reserved N/A R N/A R N/A R IS R/W 4 3 2 1 DR[2:0] IS R/W IS R/W 0 N/A R 11 IS R/W 10 20 19 18 17 PPCM[2:0] IS R/W 9 IS R/W 8 16 27 26 25 24 HcRhDescriptorB Register: bit description Symbol PPCM[2:0] Description reserved PortPowerControlMask: Each bit indicates whether a port is affected by a global power control command when PowerSwitchingMode is set. When set, the port's power state is only affected by per-port power control (Set/ClearPortPower). When cleared, the port is controlled by the global power switch (Set/ClearGlobalPower). If the device is configured to global switching mode (PowerSwitchingMode = 0), this field is not valid. Bit 0 -- reserved Bit 1 -- Ganged-power mask on Port #1 Bit 2 -- Ganged-power mask on Port #2 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 55 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcRhDescriptorB Register: bit description...continued Symbol DR[2:0] Description reserved DeviceRemovable: Each bit is dedicated to a port of the Root Hub. When cleared, the attached device is removable. When set, the attached device is not removable. Bit 0 -- reserved Bit 1 -- Device attached to Port #1 Bit 2 -- Device attached to Port #2 Table 31: Bit 15 to 3 2 to 0 10.3.3 HcRhStatus Register (R/W: 14H/94H) The HcRhStatus Register is divided into two parts. The lower word of a DWORD represents the Hub Status field and the upper word represents the Hub Status Change field. Reserved bits should always be written as logic 0. Code (Hex): 14 -- read Code (Hex): 94 -- write Table 32: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcRhStatus Register: bit allocation 31 CRWE 0 W 23 0 R 15 DRWE 0 R/W 7 0 R 0 R 6 0 R 0 R 5 reserved 0 R 0 R 0 R 0 R 0 R 4 0 R 22 0 R 14 0 R 21 reserved 0 R 13 0 R 12 0 R 11 reserved 0 R 3 0 R 2 0 R 1 OCI 0 R 0 R 0 LPS 0 R/W 0 R 10 0 R 20 30 29 28 27 reserved 0 R 19 0 R 18 0 R 17 OCIC 0 R/W 9 0 R 16 LPSC 0 R/W 8 26 25 24 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 56 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcRhStatus Register: bit description Symbol CRWE CCIC Description On write--ClearRemoteWakeupEnable: Writing a logic 1 clears DeviceRemoveWakeupEnable. Writing a logic 0 has no effect. reserved OverCurrentIndicatorChange: This bit is set by hardware when a change has occurred to the OCI field of this register. The HCD clears this bit by writing a logic 1. Writing a logic 0 has no effect. On read--LocalPowerStatusChange: The Root Hub does not support the local power status feature. Therefore, this bit is always read as logic 0. On write--SetGlobalPower: In global power mode (PowerSwitchingMode=0), this bit is written to logic 1 to turn on power to all ports (clear PortPowerStatus). In per-port power mode, it sets PortPowerStatus only on ports whose bit PortPowerControlMask is not set. Writing a logic 0 has no effect. Table 33: Bit 31 30 to 18 17 16 LPSC 15 DRWE On read--DeviceRemoteWakeupEnable: This bit enables the bit ConnectStatusChange as a resume event, causing a state transition USBSuspend to USBResume and setting the ResumeDetected interrupt. 0 -- ConnectStatusChange is not a remote wake-up event 1 -- ConnectStatusChange is a remote wake-up event On write--SetRemoteWakeupEnable: Writing a logic 1 sets DeviceRemoveWakeupEnable. Writing a logic 0 has no effect. 14 to 2 1 OCI reserved OverCurrentIndicator: This bit reports overcurrent conditions when global reporting is implemented. When set, an overcurrent condition exists. When clear, all power operations are normal. If per-port overcurrent protection is implemented this bit is always logic 0. On read--LocalPowerStatus: The Root Hub does not support the local power status feature. Therefore, this bit is always read as logic 0. On write--ClearGlobalPower: In global power mode (PowerSwitchingMode = 0), this bit is written to logic 1 to turn off power to all ports (clear PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing a logic 0 has no effect. 0 LPS 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 57 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10.3.4 HcRhPortStatus[1:2] Register (R/W [1]:15H/95H, [2]: 16H/96H) The HcRhPortStatus[1:2] Register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status, whereas the upper word reflects the status change bits. Some status bits are implemented with special write behavior. If a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. Reserved bits should always be written logic 0. Code (Hex): [1] = 15, [2] = 16 -- read Code (Hex): [1] = 95, [2] = 96 -- write Table 34: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcRhPortStatus[1:2] Register: bit allocation 31 30 29 28 reserved 00H R/W 23 0 R/W 15 0 R/W 7 0 R/W 22 reserved 0 R/W 14 0 R/W 6 reserved 0 R/W Table 35: Bit 31 to 21 20 0 R/W 0 R/W 13 reserved 0 R/W 5 0 R/W 4 PRS 0 R/W 0 R/W 3 POCI 0 R/W 0 R/W 2 PSS 0 R/W 21 20 PRSC 0 R/W 12 19 OCIC 0 R/W 11 18 PSSC 0 R/W 10 17 PESC 0 R/W 9 LSDA 0 R/W 1 PES 0 R/W 16 CSC 0 R/W 8 PPS 0 R/W 0 CCS 0 R/W 27 26 25 24 HcRhPortStatus[1:2] Register: bit description Symbol PRSC Description reserved PortResetStatusChange: This bit is set at the end of the 10 ms port reset signal. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. 0 -- port reset is not complete 1 -- port reset is complete 19 OCIC PortOverCurrentIndicatorChange: This bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. 0 -- no change in PortOverCurrentIndicator 1 -- PortOverCurrentIndicator has changed 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 58 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcRhPortStatus[1:2] Register: bit description...continued Symbol PSSC Description PortSuspendStatusChange: This bit is set when the full resume sequence has been completed. This sequence includes the 20 s resume pulse, LS EOP, and 3 ms re-synchronization delay. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. This bit is also cleared when ResetStatusChange is set. 0 -- resume is not complete 1 -- resume is complete Table 35: Bit 18 17 PESC PortEnableStatusChange: This bit is set when hardware events cause the PortEnableStatus bit to be cleared. Changes from HCD writes do not set this bit. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. 0 -- no change in PortEnableStatus 1 -- change in PortEnableStatus 16 CSC ConnectStatusChange: This bit is set whenever a connect or disconnect event occurs. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. If CurrentConnectStatus is cleared when a SetPortReset, SetPortEnable, or SetPortSuspend write occurs, this bit is set to force the driver to re-evaluate the connection status since these writes should not occur if the port is disconnected. 0 -- no change in CurrentConnectStatus 1 -- change in CurrentConnectStatus Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub reset to inform the system that the device is connected. 15 to 10 9 LSDA reserved (read) LowSpeedDeviceAttached: This bit indicates the speed of the device connected to this port. When set, a low-speed device is connected to this port. When clear, a full-speed device is connected to this port. This field is valid only when the CurrentConnectStatus is set. 0 -- full-speed device attached 1 -- low-speed device attached (write) ClearPortPower: The HCD clears the PortPowerStatus bit by writing a logic 1 to this bit. Writing a logic 0 has no effect. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 59 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcRhPortStatus[1:2] Register: bit description...continued Symbol PPS Description (read) PortPowerStatus: This bit reflects the port power status, regardless of the type of power switching implemented. This bit is cleared if an overcurrent condition is detected. The HCD sets this bit by writing SetPortPower or SetGlobalPower. The HCD clears this bit by writing ClearPortPower or ClearGlobalPower. Which power control switches are enabled is determined by PowerSwitchingMode. In the global switching mode (PowerSwitchingMode = 0), only Set/ClearGlobalPower controls this bit. In per-port power switching (PowerSwitchingMode = 1), if the PortPowerControlMask[NDP] bit for the port is set, only Set/ClearPortPower commands are enabled. If the mask is not set, only Set/ClearGlobalPower commands are enabled. When port power is disabled, CurrentConnectStatus, PortEnableStatus, PortSuspendStatus, and PortResetStatus should be reset. 0 -- port power is off 1 -- port power is on (write) SetPortPower: The HCD writes a logic 1 to set the PortPowerStatus bit. Writing a logic 0 has no effect. Remark: This bit always reads logic 1 if power switching is not supported. Table 35: Bit 8 7 to 5 4 PRS reserved (read) PortResetStatus: When this bit is set by a write to SetPortReset, port reset signaling is asserted. When reset is completed, this bit is cleared when PortResetStatusChange is set. This bit cannot be set if CurrentConnectStatus is cleared. 0 -- port reset signal is not active 1 -- port reset signal is active (write) SetPortReset: The HCD sets the port reset signaling by writing a logic 1 to this bit. Writing a logic 0 has no effect. If CurrentConnectStatus is cleared, this write does not set PortResetStatus but instead sets ConnectStatusChange. This informs the driver that it attempted to reset a disconnected port. 3 POCI (read) PortOverCurrentIndicator: This bit is valid only when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. If per-port overcurrent reporting is not supported, this bit is set to logic 0. If cleared, all power operations are normal for this port. If set, an overcurrent condition exists on this port. This bit always reflects the overcurrent input signal 0 -- no overcurrent condition 1 -- overcurrent condition detected (write) ClearSuspendStatus: The HCD writes a logic 1 to initiate a resume. Writing a logic 0 has no effect. A resume is initiated only if PortSuspendStatus is set. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 60 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcRhPortStatus[1:2] Register: bit description...continued Symbol PSS Description (read) PortSuspendStatus: This bit indicates whether the port is suspended or in the resume sequence. It is set by a SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume interval. This bit cannot be set if CurrentConnectStatus is cleared. This bit is also cleared when PortResetStatusChange is set at the end of the port reset or when the HC is placed in the USBResume state. If an upstream resume is in progress, it is propagated to the HC. 0 -- port is not suspended 1 -- port is suspended (write) SetPortSuspend: The HCD sets the PortSuspendStatus bit by writing a logic 1 to this bit. Writing a logic 0 has no effect. If CurrentConnectStatus is cleared, this write action does not set PortSuspendStatus; instead it sets ConnectStatusChange. This informs the driver that it attempted to suspend a disconnected port. Table 35: Bit 2 1 PES (read) PortEnableStatus: This bit indicates whether the port is enabled or disabled. The Root Hub can clear this bit when an overcurrent condition, disconnect event, switched-off power, or operational bus error such as babble is detected. This change also causes PortEnabledStatusChange to be set. The HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus is cleared. This bit is also set at the completion of a port reset when ResetStatusChange is set or port is suspended when SuspendStatusChange is set. 0 -- port is disabled 1 -- port is enabled (write) SetPortEnable: The HCD sets PortEnableStatus by writing a logic 1. Writing a logic 0 has no effect. If CurrentConnectStatus is cleared, this write does not set PortEnableStatus, but instead sets ConnectStatusChange. This informs the driver that it attempted to enable a disconnected port. 0 CCS (read) CurrentConnectStatus: This bit reflects the current state of the downstream port. 0 -- no device connected 1 -- device connected (write) ClearPortEnable: The HCD writes a logic 1 to this bit to clear the PortEnableStatus bit. Writing a logic 0 has no effect. CurrentConnectStatus is not affected by any write. Remark: This bit always reads logic 1 when the attached device is nonremovable (DeviceRemoveable[NDP]). 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 61 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10.4 HC DMA and interrupt control registers 10.4.1 HcHardwareConfiguration Register (R/W: 20H/A0H) 1. Bit 0, InterruptPinEnable, is used as pin INT1's master interrupt enable. This bit should be used together with the register HcPInterruptEnable to enable pin INT1. 2. Bits 4 and 3 are fixed at logic 0 and logic 1 for the ISP1161A. Code (Hex): 20 -- read Code (Hex): A0 -- write Table 36: Bit Symbol HcHardwareConfiguration Register: bit allocation 15 14 reserved 13 12 2_Down streamPort 15K resistorsel 0 R/W 5 DREQOut putPolarity 1 R/W 0 R/W 4 11 Suspend ClkNotStop 10 AnalogOC Enable 9 reserved 8 DACKMode Reset Access Bit Symbol Reset Access Table 37: Bit 15 to 13 12 0 R/W 7 EOTInput Polarity 0 R/W 0 R/W 6 DACKInput Polarity 0 R/W 0 R/W 3 0 R/W 2 InterruptOut putPolarity 0 R/W 0 R/W 1 InterruptPi nTrigger 0 R/W 0 R/W 0 InterruptPin Enable 0 R/W DataBusWidth[1:0] 0 R/W 1 R/W HcHardwareConfiguration Register: bit description Symbol 2_DownstreamPort15KresistorSel Description reserved 0 -- use external 15 k resistors for downstream ports. Power-up value 1 -- built-in resistors for downstream ports 0 -- clock can be stopped 1 -- clock can not be stopped 0 -- use external OC detection. Digital input 1 -- use on-chip OC detection. Analog input reserved 0 -- normal operation. DACK1 is used with read and write signals. Power-up value 1 -- reserved 0 -- active LOW. Power-up value 1 -- active HIGH 0 -- active LOW. Power-up value 1 -- reserved 11 10 9 8 SuspendClkNotStop AnalogOCEnable DACKMode 7 6 EOTInputPolarity DACKInputPolarity 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 62 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 37: Bit 5 4 to 3 2 1 0 HcHardwareConfiguration Register: bit description...continued Symbol DREQOutputPolarity DataBusWidth[1:0] InterruptOutputPolarity InterruptPinTrigger InterruptPinEnable Description 0 -- active LOW 1 -- active HIGH. Power-up value 01 -- 16 bits Others -- reserved 0 -- active LOW. Power-up value 1 -- active HIGH 0 -- interrupt is level-triggered. Power-up value 1 -- interrupt is edge-triggered 0 -- INT1 is disabled. Power-up value 1 -- pin INT1 is enabled 10.4.2 HcDMAConfiguration Register (R/W: 21H/A1H) Code (Hex): 21 -- read Code (Hex): A1 -- write Table 38: Bit Symbol Reset Access Bit Symbol Reset Access HcDMAConfiguration Register: bit allocation 15 14 13 12 reserved 00H R/W 7 reserved 0 R/W 6 5 4 DMA Enable 0 R/W 3 reserved 0 R/W 2 DMACount erSelect 0 R/W 1 ITL_ATL_ DataSelect 0 R/W 0 DMARead WriteSelect 0 R/W BurstLen[1:0] 0 R/W Table 39: Bit 15 to 7 6 to 5 0 R/W 11 10 9 8 HcDMAConfiguration Register: bit description Symbol Description reserved BurstLen[1:0] 00 -- single-cycle burst DMA 01 -- 4-cycle burst DMA 10 -- 8-cycle burst DMA 11 -- reserved 4 DMAEnable 0 -- DMA is terminated 1 -- DMA is enabled This bit will be reset to zero when DMA transfer is completed 3 - reserved 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 63 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcDMAConfiguration Register: bit description...continued Symbol DMACounter Select Description 0 -- DMA counter not used. External EOT must be used 1 -- Enables the DMA counter for DMA transfer. HcTransferCounter Register must be filled with non-zero values for DREQ1 to be raised after bit DMA Enable is set 0 -- ITL buffer RAM selected for ITL data 1 -- ATL buffer RAM selected for ATL data 0 -- read from the HC FIFO buffer RAM 1 -- write to the HC FIFO buffer RAM Table 39: Bit 2 1 0 ITL_ATL_ DataSelect DMARead WriteSelect 10.4.3 HcTransferCounter Register (R/W: 22H/A2H) This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer, the number of bytes being read or written to the Isochronous Transfer List (ITL) or Acknowledged Transfer List (ATL) buffer RAM must be written into this register. For a DMA transfer, the number of bytes must be written into this register as well. However, for this counter to be read into the DMA counter, the HCD must set bit 2 of the HcDMAConfiguration Register. The counter value for ATL must not be greater than 1000H, and for ITL it must not be greater than 800H. When the byte count of the data transfer reaches this value, the HC will generate an internal EOT signal to set bit 2 (AllEOInterrupt) of the HcPInterrupt Register, and also update the HcBufferStatus Register. Code (Hex): 22 -- read Code (Hex): A2 -- write Table 40: Bit Symbol Reset Access Bit Symbol Reset Access HcTransferCounter Register: bit allocation 15 14 13 12 00H R/W 7 6 5 4 00H R/W Table 41: Bit 15 to 0 HcTransferCounter Register: bit description Symbol Counter value Description The number of data bytes to be read to or written from RAM 3 2 1 0 Counter value 11 10 9 8 Counter value 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 64 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10.4.4 HcPInterrupt Register (R/W: 24H/A4H) All the bits in this register will be active on power-on reset. However, none of the active bits will cause an interrupt on the interrupt pin (INT1) unless they are set by the respective bits in the HcPInterruptEnable Register, and together with bit 0 of the HcHardwareConfiguration Register. After this register (24H read) is read, the bits that are active will not be reset, until logic 1 is written to the bits in this register (A4H - write) to clear it. To clear all the enabled bits in this register, the HCD must write FFH to this register. Code (Hex): 24 -- read Code (Hex): A4 -- write Table 42: Bit Symbol Reset Access Bit Symbol Reset Access HcPInterrupt Register: bit allocation 15 14 13 12 reserved 00H R/W 7 reserved 0 R/W 6 ClkReady 0 R/W Table 43: Bit 15 to 7 6 5 HC Suspended 0 R/W 4 OPR_Reg 0 R/W 3 reserved 0 R/W 2 AllEOT Interrupt 0 R/W 1 ATLInt 0 R/W 0 SOFITLInt 0 R/W 11 10 9 8 HcPInterrupt Register: bit description Symbol ClkReady Description reserved 0 -- no event 1 -- clock is ready. After a wake-up is sent, there is a wait for clock ready. (Maximum is 1 ms, and typical is 160 s) 5 HC 0 -- no event Suspended 1 -- the HC has been suspended and no USB activity is sent from the microprocessor for each ms. When the microprocessor wants to suspend the HC, the microprocessor must write to the HcControl Register. And when all downstream devices are suspended, then the HC stops sending SOF; the HC is suspended by having the HcControl Register written into. OPR_Reg 0 -- no event 1 -- There are interrupts from HC side. Need to read HcControl and HcInterrupt Registers to detect type of interrupt on the HC (if the HC requires the Operational Register to be updated) 4 3 2 AllEOT Interrupt reserved 0 -- no event 1 -- implies that data transfer has been completed via PIO transfer or DMA transfer. Occurrence of internal or external EOT will set this bit. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 65 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcPInterrupt Register: bit description...continued Symbol ATLInt Description 0 -- no event 1 -- implies that the microprocessor must read ATL data from the HC. This requires that the HcBufferStatus Register must first be read. The time for this interrupt depends on the number of clocks bit set for USB activities in each ms. Table 43: Bit 1 0 SOFITLInt 0 -- no event 1 -- implies that SOF indicates the 1 ms mark. The ITL buffer that the HC has handled must be read. To know the ITL buffer status, the HcBufferStatus Register must first be read. This is for the microprocessor to get ISO data to or from the HC. For more information, see the 6th paragraph in Section 9.5. 10.4.5 HcPInterruptEnable Register (R/W: 25H/A5H) The bits 6:0 in this register are the same as those in the HcPInterrupt Register. They are used together with bit 0 of the HcHardwareConfiguration Register to enable or disable the bits in the HcPInterrupt Register. At power-on, all bits in this register are masked with logic 0. This means no interrupt request output on the interrupt pin INT1 can be generated. When the bit is set to logic 1, the interrupt for the bit is not masked but enabled. Code (Hex): 25 -- read Code (Hex): A5 -- write Table 44: Bit Symbol Reset Access Bit Symbol HcPInterruptEnable Register: bit allocation 15 14 13 12 reserved 00H R/W 7 reserved 6 ClkReady 5 HC Suspended Enable 0 R/W 4 OPR Interrupt Enable 0 R/W 3 reserved 2 EOT Interrupt Enable 0 R/W 1 ATL Interrupt Enable 0 R/W 0 SOF Interrupt Enable 0 R/W 11 10 9 8 Reset Access 0 R/W 0 R/W Table 45: Bit 15 to 7 6 0 R/W HcPInterruptEnable Register: bit description Symbol ClkReady Description reserved 0 -- power-up value 1 -- enables Clkready interrupt 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 66 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller HcPInterruptEnable Register: bit description...continued Symbol Description HC 0 -- power-up value Suspended 1 -- enables HC suspended interrupt. When the microprocessor Enable wants to suspend the HC, the microprocessor must write to the HcControl Register. And when all downstream devices are suspended, then the HC stops sending SOF; the HC is suspended by having the HcControl Register written into. OPR Interrupt Enable EOT Interrupt Enable ATL Interrupt Enable SOF Interrupt Enable 0 -- power-up value 1 -- enables the 32-bit Operational Register's interrupt (if the HC requires the Operational Register to be updated) reserved 0 -- power-up value 1 -- enables the EOT interrupt which indicates an end of a read/write transfer 0 -- power-up value 1 -- enables ATL interrupt. The time for this interrupt depends on the number of clock bits set for USB activities in each ms. 0 -- power-up value 1 -- enables the interrupt bit due to SOF (for the microprocessor DMA to get ISO data from the HC by first accessing the HcDMAConfiguration Register) Table 45: Bit 5 4 3 2 1 0 10.5 HC miscellaneous registers 10.5.1 HcChipID Register (R: 27H) Read this register to get the ID of the ISP1161A silicon chip. The high byte stands for the product name (here 61H stands for ISP1161A). The low byte indicates the revision number of the product including engineering samples (here 10H means revision 1, that is ES1 of ISP1161A). Code (Hex): 27 -- read Table 46: Bit Symbol Reset Access Bit Symbol Reset Access Table 47: Bit 15 to 0 7 6 5 4 ChipID[7:0] 10H R HcChipID Register: bit description Symbol ChipID[15:0] Description ISP1161A's chip ID HcChipID Register: bit allocation 15 14 13 12 61H R 3 2 1 0 11 10 9 8 ChipID[15:8] 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 67 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10.5.2 HcScratch Register (R/W: 28H/A8H) This register is for the HCD to save and restore values when required. Code (Hex): 28 -- read Code (Hex): A8 -- write Table 48: Bit Symbol Reset Access Bit Symbol Reset Access HcScratch Register: bit allocation 15 14 13 12 00H R/W 7 6 5 4 Scratch[7:0] 00H R/W Table 49: Bit 15 to 0 HcScratch Register: bit description Symbol Scratch[15:0] Description Scratch Register value 3 2 1 0 11 10 9 8 Scratch[15:8] 10.5.3 HcSoftwareReset Register (W: A9H) This register provides a means for software reset of the HC. To reset the HC, the HCD must write a reset value of F6H to this register. Upon receiving the reset value, the HC resets all the registers except its buffer memory. Code (Hex): A9 -- write Table 50: Bit Symbol Reset Access Bit Symbol Reset Access HcSoftwareReset Register: bit allocation 15 14 13 12 00H W 7 6 5 4 Reset[7:0] 00H W Table 51: Bit 15 to 0 HcSoftwareReset Register: bit description Symbol Description Reset[15:0] Writing a reset value of F6H will cause the HC to reset all the registers except its buffer memory. 3 2 1 0 11 10 9 8 Reset[15:8] 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 68 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10.6 HC buffer RAM control registers 10.6.1 HcITLBufferLength Register (R/W: 2AH/AAH) Write to this register to assign the ITL buffer size in bytes: ITL0 and ITL1 are assigned the same value. For example, if HcITLBufferLength Register is set to 2 kbytes, then ITL0 and ITL1 would be allocated 2 kbytes each. Must follow the formula: ATL buffer length + 2 x (ITL buffer size) 1000H (that is, 4 kbytes) where: ITL buffer size = ITL0 buffer length = ITL1 buffer length Code (Hex): 2A -- read Code (Hex): AA -- write Table 52: Bit Symbol Reset Access Bit Symbol Reset Access Table 53: Bit 15 to 0 7 6 5 4 00H R/W HcITLBufferLength Register: bit description Symbol ITLBufferLength[15:0] Description Assign ITL buffer length HcITLBufferLength Register: bit allocation 15 14 13 12 00H R/W 3 2 1 0 ITLBufferLength[7:0] 11 10 9 8 ITLBufferLength[15:8] 10.6.2 HcATLBufferLength Register (R/W: 2BH/ABH) Write to this register to assign ATL buffer size. Code (Hex): 2B -- read Code (Hex): AB -- write Remark: The maximum total RAM size is 1000H (4096 in decimal) bytes. That means ITL0 (length) + ITL1 (length) + ATL (length) 1000H bytes. For example, if ATL buffer length has been set to be 800H, then the maximum ITL buffer length can only be set as 400H. Table 54: Bit Symbol Reset Access HcATLBufferLength Register: bit allocation 15 14 13 12 00H R/W 11 10 9 8 ATLBufferLength[15:8] 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 69 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 5 4 00H R/W 3 2 1 0 Bit Symbol Reset Access 7 6 ATLBufferLength[7:0] Table 55: Bit 15 to 0 HcATLBufferLength Register: bit description Symbol ATLBufferLength[15:0] Description Assign ATL buffer length 10.6.3 HcBufferStatus Register (R: 2CH) Code (Hex): 2C -- read Table 56: Bit Symbol Reset Access Bit Symbol Reset Access HcBufferStatus Register: bit allocation 15 14 13 12 reserved 00H R 7 reserved 0 R 0 R Table 57: Bit 15 to 6 5 4 3 2 1 0 6 5 ATLBuffer Done 0 R 4 ITL1Buffer Done 0 R 3 ITL0Buffer Done 0 R 2 ATLBuffer Full 0 R 1 ITL1Buffer Full 0 R 0 ITL0Buffer Full 0 R 11 10 9 8 HcBufferStatus Register: bit description Symbol ATLBuffer Done ITL1Buffer Done ITL0Buffer Done ATLBuffer Full ITL1Buffer Full ITL0Buffer Full Description reserved 0 -- ATL Buffer not read by HC yet 1 -- ATL Buffer read by HC 0 -- ITL1 Buffer not read by HC yet 1 -- ITL1 Buffer read by HC 0 -- 1TL0 Buffer not read by HC yet 1 -- 1TL0 Buffer read by HC 0 -- ATL Buffer is empty 1 -- ATL Buffer is full 0 -- 1TL1 Buffer is empty 1 -- 1TL1 Buffer is full 0 -- ITL0 Buffer is empty 1 -- ITL0 Buffer is full 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 70 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10.6.4 HcReadBackITL0Length Register (R: 2DH) This register's value stands for the current number of data bytes inside an ITL0 buffer to be read back by the microprocessor. The HCD must set the HcTransferCounter equivalent to this value before reading back the ITL0 buffer RAM. Code (Hex): 2D -- read Table 58: Bit Symbol Reset Access Bit Symbol Reset Access HcReadBackITL0Length Register: bit allocation 15 14 13 12 00H R 7 6 5 4 00H R Table 59: Bit 15 to 0 HcReadBackITL0Length Register: bit description Symbol RdITL0BufferLength[15:0] Description The number of bytes for ITL0 data to be read back by the microprocessor 3 2 1 0 RdITL0BufferLength[7:0] 11 10 9 8 RdITL0BufferLength[15:8] 10.6.5 HcReadBackITL1Length Register (R: 2EH) This register's value stands for the current number of data bytes inside the ITL1 buffer to be read back by the microprocessor. The HCD must set the HcTransferCounter equivalent to this value before reading back the ITL1 buffer RAM. Code (Hex): 2E -- read Table 60: Bit Symbol Reset Access Bit Symbol Reset Access HcReadBackITL1Length Register: bit allocation 15 14 13 12 00H R 7 6 5 4 OOH R Table 61: Bit 15 to 0 HcReadBackITL1Length Register: bit description Symbol Description RdITL1BufferLength[15:0] The number of bytes for ITL1 data to be read back by the microprocessor 3 2 1 0 RdITL1BufferLength[7:0] 11 10 9 8 RdITL1BufferLength[15:8] 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 71 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 10.6.6 HcITLBufferPort Register (R/W: 40H/C0H) This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that comes from the ITL buffer RAM's even address. The bits 7:0 contain the data byte that comes from the ITL buffer RAM's odd address. Code (Hex): 40 -- read Code (Hex): C0 -- write Table 62: Bit Symbol Reset Access Bit Symbol Reset Access HcITLBufferPort Register: bit allocation 15 14 13 12 OOH R/W 7 6 5 4 00H R/W Table 63: Bit 15 to 0 HcITLBufferPort Register: bit description Symbol DataWord[15:0] Description read/write ITL buffer RAM's two data bytes. 3 2 1 0 DataWord[7:0] 11 10 9 8 DataWord[15:8] The HCD must set the byte count into the HcTransferCounter Register and check the HcBufferStatus Register before reading from or writing to the buffer. The HCD must write the command (40H for read, C0H for write) once only, and then read or write both bytes of the data word. After every read/write, the pointer of ITL buffer RAM will be automatically increased by two to point to the next data word until it reaches the value of HcTransferCounter Register; otherwise, an internal EOT signal is not generated to set the bit 2 (AllEOTInterrupt) of the HcPInterrupt Register and update the HcBufferStatus Register. The HCD must take care of the fact that the internal buffer RAM is organized in bytes. The HCD must write the byte count into the HcTransferCounter Register, but the HCD reads or writes the buffer RAM by 16 bits (by 1 data word). 10.6.7 HcATLBufferPort Register (R/W: 41H/C1H) This is the ATL buffer RAM read/write port. The bits 15:8 contain the data byte that comes from the Acknowledged Transfer List (ATL) buffer RAM's odd address. Bits 7:0 contain the data byte that comes from the ATL buffer RAM's even address. Code (Hex): 41 -- read Code (Hex): C1 -- write Table 64: Bit Symbol Reset Access HcATLBufferPort Register: bit allocation 15 14 13 12 00H R/W 11 10 9 8 DataWord[15:8] 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 72 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 5 4 00H R/W 3 2 1 0 Bit Symbol Reset Access 7 6 DataWord[7:0] Table 65: Bit 15 to 0 HcATLBufferPort Register: bit description Symbol DataWord[15:0] Description read/write ATL buffer RAM's two data bytes. The HCD must set the byte count into the HcTransferCounter Register and check the HcBufferStatus Register before reading from or writing to the buffer. The HCD must write the command (41H for read, C1H for write) once only, and then read or write both bytes of the data word. After every read/write, the pointer of ATL buffer RAM will be automatically increased by two to point to the next data word until it reaches the value of HcTransferCounter Register; otherwise, an internal EOT signal is not generated to set the bit 2 (AllEOTInterrupt) of the HcPInterrupt Register and update the HcBufferStatus Register. The HCD must take care of the difference: the internal buffer RAM is organized in bytes, so the HCD must write the byte count into the HcTransferCounter Register, but the HCD reads or writes the buffer RAM by 16 bits (by 1 data word). 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 73 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 11. USB device controller (DC) The Device Controller (DC) in the ISP1161A is based on the Philips ISP1181B USB Full-Speed Interface Device IC. The functionality, commands, and register sets are the same as ISP1181B in 16-bit bus mode. If there is any differences between the ISP1181B and ISP1161A datasheets, in terms of the DC functionality, the ISP1161A datasheet supersedes content in the ISP1181B datasheet. In general the DC in an ISP1161A provides 16 endpoints for USB device implementation. Each endpoint can be allocated an amount of RAM space in the on-chip Ping-Pong buffer RAM. Remark: Note: the Ping-Pong buffer RAM for the DC is independent of the buffer RAM in the HC. When the buffer RAM is full, the DC will transfer the data in the buffer RAM to the USB bus. When the buffer RAM is empty, an interrupt is generated to notify the microprocessor to feed in the data. The transfer of data between the microprocessor and the DC can be done in Programmed I/O (PIO) mode or in DMA mode. 11.1 DC data transfer operation The following session explains how the DC of an ISP1161A handles an IN data transfer and an OUT data transfer. In the Device mode, ISP1161A acts as a USB device: an IN data transfer means transfer from ISP1161A to an external USB Host (through the upstream port) and an OUT transfer means transfer from external USB Host to ISP1161A. 11.1.1 IN data transfer * The arrival of the IN token is detected by the SIE by decoding the PID. * The SIE also checks for the device number and endpoint number and verifies whether they are acceptable. * If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus Register. If the endpoint is full, the contents of the FIFO are sent during the data phase, otherwise a Not Acknowledge (NAK) handshake is sent. * After the data phase, the SIE expects a handshake (ACK) from the host (except for ISO endpoints). * On receiving the handshake (ACK), the SIE updates the contents of the DcEndpointStatus Register and the DcInterrupt Register, which in turn generates an interrupt to the microprocessor. For ISO endpoints, the interrupt register is updated as soon as data is sent because there is no handshake phase. * On receiving an interrupt, the microprocessor reads the DcInterrupt Register. It will know which endpoint has generated the interrupt and reads the contents of the corresponding DcEndpointStatus Register. If the buffer is empty, it fills up the buffer, so that data can be sent by the SIE at the next IN token phase. 11.1.2 OUT data transfer * The arrival of the OUT token is detected by the SIE by decoding the PID. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 74 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller * The SIE also checks for the device number and endpoint number and verifies whether they are acceptable. * If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus Register. If the endpoint is empty, the data from USB is stored to FIFO during the data phase, otherwise a NAK handshake is sent. * After the data phase, the SIE sends a handshake (ACK) to the host (except for ISO endpoints). * The SIE updates the contents of the DcEndpointStatus Register and the DcInterrupt Register, which in turn generates an interrupt to the microprocessor. For ISO endpoints, the interrupt register is updated as soon as data is received because there is no handshake phase. * On receiving interrupt, the microprocessor reads the DcInterrupt Register. It will know which endpoint has generated the interrupt and reads the content of the corresponding DcEndpointStatus Register. If the buffer is full, it empties the buffer, so that data can be received by the SIE at the next OUT token phase. 11.2 Device DMA transfer 11.2.1 DMA for IN endpoint (internal DC to external USB host) When the internal DMA handler is enabled and at least one buffer (Ping or Pong) is free, the DREQ2 line is asserted. The external DMA controller then starts negotiating for control of the bus. As soon as it has access, it asserts the DACK2 line and starts writing data. The burst length is programmable. When the number of bytes equal to the burst length has been written, the DREQ2 line is de-asserted. As a result, the DMA controller de-asserts the DACK2 line and releases the bus. At that moment the whole cycle restarts for the next burst. When the buffer is full, the DREQ2 line will be de-asserted and the buffer is validated (which means that it will be sent to the host when the next IN token comes in). When the DMA transfer is terminated, the buffer is also validated (even if it is not full). A DMA transfer is terminated when any of the following conditions are met: * the DMA count is complete * DMAEN = 0 * the DMA controller asserts EOT. 11.2.2 DMA for OUT endpoint (external USB host to internal DC) When the internal DMA handler is enabled and at least one buffer is full, the DREQ2 line is asserted. The external DMA controller then starts negotiating for control of the bus, and as soon as it has access, it asserts the DACK2 line and starts reading the data. The burst length is programmable. When the number of bytes equal to the burst length has been read, the DREQ2 line is de-asserted. As a result, the DMA controller de-asserts the DACK2 line and releases the bus. At that moment the whole cycle restarts for the next burst. When all data are read, the DREQ2 line will be de-asserted and the buffer is cleared (which means that it can be overwritten when a new packet comes in). 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 75 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller A DMA transfer is terminated when any of the following conditions are met: * the DMA count is complete * DMAEN = 0 * the DMA controller asserts EOT. When the DMA transfer is terminated, the buffer is also cleared (even if the data is not completely read) and the DMA handler is disabled automatically. For the next DMA transfer, the DMA controller as well as the DMA handler must be re-enabled. 11.3 Endpoint descriptions 11.3.1 Endpoints with programmable FIFO size Each USB device is logically composed of several independent endpoints. An endpoint acts as a terminus of a communication flow between the host and the device. At design time each endpoint is assigned a unique number (endpoint identifier, see Table 66). The combination of the device address (given by the host during enumeration), the endpoint number and the transfer direction allows each endpoint to be uniquely referenced. The DC has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 configurable endpoints, which can be individually defined as interrupt/bulk/isochronous, IN or OUT. Each enabled endpoint has an associated FIFO, which can be accessed either via the Programmed I/O interface or via DMA. 11.3.2 Endpoint access Table 66 lists the endpoint access modes and programmability. All endpoints support I/O mode access. Endpoints 1 to 14 also support DMA access. DC FIFO DMA access is selected and enabled via bits EPIDX[3:0] and DMAEN of the DcDMAConfiguration Register. A detailed description of the DC DMA operation is given in Section 12. Table 66: Endpoint identifier 0 0 1 2 3 4 5 6 7 8 9 10 11 9397 750 09568 Endpoint access and programmability FIFO size (bytes) 64 (fixed) 64 (fixed) programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable Double buffering no no supported supported supported supported supported supported supported supported supported supported supported I/O mode access yes yes supported supported supported supported supported supported supported supported supported supported supported DMA mode access no no supported supported supported supported supported supported supported supported supported supported supported Endpoint type control OUT[1] control IN[1] programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 76 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 66: Endpoint identifier 12 13 14 [1] [2] [3] Endpoint access and programmability...continued FIFO size (bytes) programmable programmable programmable Double buffering supported supported supported I/O mode access supported supported supported DMA mode access supported supported supported Endpoint type programmable programmable programmable IN: input for the USB host (ISP1161A transmits); OUT: output from the USB host (ISP1161A receives). The data flow direction is determined by bit EPDIR in the DcEndpointConfiguration Register; seeSection 13.1.1. The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. 11.3.3 Endpoint FIFO size The size of the FIFO determines the maximum packet size that the hardware can support for a given endpoint. Only enabled endpoints are allocated space in the shared FIFO storage, disabled endpoints have zero bytes. Table 67 lists the programmable FIFO sizes. The following bits in the Endpoint Configuration Register (ECR) affect FIFO allocation: * Endpoint enable bit (FIFOEN) * Size bits of an enabled endpoint (FFOSZ[3:0]) * Isochronous bit of an enabled endpoint (FFOISO). Remark: Register changes that affect the allocation of the shared FIFO storage among endpoints must not be made while valid data is present in any FIFO of the enabled endpoints. Such changes will render all FIFO contents undefined. Table 67: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Programmable FIFO size Non-isochronous 8 bytes 16 bytes 32 bytes 64 bytes reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Isochronous 16 bytes 32 bytes 48 bytes 64 bytes 96 bytes 128 bytes 160 bytes 192 bytes 256 bytes 320 bytes 384 bytes 512 bytes 640 bytes 768 bytes 896 bytes 1023 bytes FFOSZ[3:0] 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 77 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Each programmable FIFO can be configured independently via its ECR, but the total physical size of all enabled endpoints (IN plus OUT) must not exceed 2462 bytes (512 bytes for non-isochronous FIFOs). Table 68 shows an example of a configuration fitting in the maximum available space of 2462 bytes. The total number of logical bytes in the example is 1311. The physical storage capacity used for double buffering is managed by the device hardware and is transparent to the user. Table 68: Memory configuration example Logical size (bytes) 64 64 1023 16 16 64 64 Endpoint description control IN (64 byte fixed) control OUT (64 byte fixed) double-buffered 1023-byte isochronous endpoint 16-byte interrupt OUT 16-byte interrupt IN double-buffered 64-byte bulk OUT double-buffered 64-byte bulk IN Physical size (bytes) 64 64 2046 16 16 128 128 11.3.4 Endpoint initialization In response to the standard USB request, Set Interface, the firmware must program all 16 ECRs of the ISP1161A's DC in sequence (see Table 66), whether the endpoints are enabled or not. The hardware will then automatically allocate FIFO storage space. If all endpoints have been configured successfully, the firmware must return an empty packet to the control IN endpoint to acknowledge success to the host. If there are errors in the endpoint configuration, the firmware must stall the control IN endpoint. When reset by hardware or via the USB bus, the ISP1161A's DC disables all endpoints and clears all ECRs, except for the control endpoint which is fixed and always enabled. Endpoint initialization can be done at any time; however, it is valid only after enumeration. 11.3.5 Endpoint I/O mode access When an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (EPn) of the DcInterrupt Register will be set by the SIE. The firmware then responds to the interrupt and selects the endpoint for processing. The endpoint interrupt bit will be cleared by reading the DcEndpointStatus Register (ESR). The ESR also contains information on the status of the endpoint buffer. For an OUT (= receive) endpoint, the packet length and packet data can be read from ISP1161A's DC using the Read Buffer command. When the whole packet has been read, the firmware sends a Clear Buffer command to enable the reception of new packets. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 78 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller For an IN (= transmit) endpoint, the packet length and data to be sent can be written to ISP1161A's DC using the Write Buffer command. When the whole packet has been written to the buffer, the firmware sends a Validate Buffer command to enable data transmission to the host. 11.3.6 Special actions on control endpoints Control endpoints require special firmware actions. The arrival of a SETUP packet flushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The microcontroller needs to re-enable these commands by sending an Acknowledge Setup command. This ensures that the last SETUP packet stays in the buffer and that no packets can be sent back to the host until the microcontroller has explicitly acknowledged that it has seen the SETUP packet. 11.4 Suspend and resume 11.4.1 Suspend conditions The ISP1161A's DC detects a `suspend' status in the following cases: * A J-state is present on the USB bus for 3 ms * VBUS is lost (weak pull-up/down on D+ and D-). With SoftConnect disabled, ISP1161A does not go into the suspend state as long as VBUS is present. ISP1161A's DC will remain in `suspend' state for at least 5 ms, before responding to external wake-up events such as global resume, bus traffic, wake-up on CS or WAKEUP. The typical timing is shown in Figure 37. GOSUSP suspend >5 ms D_WAKEUP 004aaa031 start detection of wake-up conditions Fig 37. DC typical suspend timing. Bus-powered devices that are suspended must not consume more than 500 A of current. This is achieved by shutting down the power to system components or supplying them with a reduced voltage. ISP1161A's DC is always in powered-off mode during `suspend' state. As a default, bit PWROFF in the DcHardwareConfiguration Register is logic 1 and this value should not be changed under any condition. This powered-off mode is explained in detail in Section "Powered-off application" on page 80. The steps leading up to `suspend' status are as follows: 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 79 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 1. Upon detection of a `wake-up' to `suspend' transition ISP1161A's DC sets bit SUSPND in the DcInterrupt Register. This will generate an interrupt if bit IESUSP in the Interrupt Enable Register is set. 2. When the firmware detects a `suspend' condition it must prepare all system components for `suspend' state: a. All signals connected to ISP1161A's DC must enter appropriate states to meet the power consumption requirements of `suspend' state. b. All input pins of ISP1161A's DC must have a CMOS logic 0 or logic 1 level. 3. In the interrupt service routine, the firmware must check the current status of the USB bus. When bit BUSTATUS in the DcInterrupt Register is logic 0, the USB bus has left `suspend' mode and the process must be aborted. Otherwise, the next step can be executed. 4. To meet the `suspend' current requirements for a bus-powered device, the internal clocks must be switched off by clearing bit CLKRUN in the DcHardwareConfiguration Register. 5. When the firmware has set and cleared the GOSUSP bit in the DcMode Register, the ISP1161A's DC enters `suspend' state. In powered-off application, the ISP1161A's DC asserts output D_SUSPEND and switches off the internal clocks (except LazyClock) after 2 ms. Powered-off application: In powered-off application (PWROFF = 1 in the DcHardwareConfiguration Register) the supply of the CPU and other parts of the circuit is removed during `suspend' state. The D_SUSPEND output is active HIGH during `suspend' state, making it suitable as a power switch control signal, e.g. for an external oscillator. Input pins of ISP1161A's DC are pulled to ground via the pin buffers. Outputs are made three-state to prevent current flowing in the application. Bi-directional pins are made three-state and must be pulled to ground externally by the application. The power supply of external pull-ups must also be removed to reduce power consumption. GOSUSP D_WAKEUP 2 ms 0.5 ms D_SUSPEND 004aaa032 Fig 38. Suspend and resume timing for powered-off application (DC side). Table 69: Pin A0 D[15:0] D_SUSPEND 9397 750 09568 Pin states in powered-off application Type I I/O (three-state) O ISP1161A's DC drives logic 1 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Appropriate state inactive Product data Rev. 01 -- 02 August 2002 80 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Pin states in powered-off application...continued Type I O I I I I I O Appropriate state inactive powered off; internally connected to ground (logic 0) externally driven [1] to logic 1 powered off; internally connected to ground (logic 0) powered off; internally connected to ground (logic 0) powered off; internally connected to ground (logic 0) powered off; internally connected to ground (logic 0) ISP1161A's DC drives logic 0, if the NOLAZY bit is set to logic 1 in the DcHardwareConfiguration Register Table 69: Pin D_WAKEUP INT2 RESET CS RD WR XTAL1 CLKOUT [1] `Externally driven' refers to logic outside the ISP1161A's DC. When external components are powered-off, it is possible that interface signals RD, WR and CS have unknown values immediately after leaving `suspend' state. To prevent corruption of its internal registers, ISP1161A's DC enables a locking mechanism once suspend is enabled. After wake up from suspend' state, all internal registers except the Unlock Register are read and write protected. A special unlock operation is needed to re-enable write access. This prevents data corruption during power-up of external components. Figure 39 shows a typical bus-powered modem application using ISP1161A's DC in powered-off mode. The SUSPEND output is used to switch off power to the microcontroller and other external circuits during `suspend' state. The ISP1161A's DC is woken up via the USB bus (global resume) or by the ring detection circuit on the telephone line. VBUS power switch VCC VCC MICROCONTROLLER USB D_DP D_DM ISP1161A D_SUSPEND D_WAKEUP RING DETECTION LINE 004aaa084 Fig 39. ISP1161A's DC SUSPEND and WAKEUP signals in a powered-off modem application. 11.4.2 Resume conditions Wake up from `suspend' state is initiated either by the USB host or by the application: * USB host: drives a K-state on the USB bus (global resume) * Application: remote wake-up via a HIGH level on input WAKEUP or a LOW level on input CS (if enabled via bit WKUPCS in the DcHardwareConfiguration Register). Wake-up on CS will work only if VBUS is present. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 81 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller The steps of a wake-up sequence are as follows: 1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, the clock signals are routed to all internal circuits of the ISP1161A's DC. 2. The D_SUSPEND output is de-asserted and the RESUME bit in the DcInterrupt Register is set. This will generate an interrupt if bit IERESUME in the Interrupt Enable Register is set. 3. Maximum 15 ms after starting the wake-up sequence, the ISP1161A's DC resumes its normal functionality. 4. In case of a remote wake-up, ISP1161A's DC drives a K-state on the USB bus for 10 ms. 5. Following the de-assertion of output D_SUSPEND, the application restores itself and other system components to normal operating mode. 6. After wake-up, the internal registers of ISP1161A's DC are read and write protected to prevent corruption by inadvertent writing during power-up of external components. The firmware must send an Unlock Device command to the ISP1161A's DC to restore its full functionality. See Section 13.3.2 for more details. 11.4.3 Control bits in suspend and resume Table 70: Register Interrupt Summary of control bits Bit SUSPND BUSTATUS Interrupt Enable Mode IESUSP SOFTCT GOSUSP DcHardwareConfiguration EXTPUL WKUPCS PWROFF Unlock all Function a transition from `awake' to `suspend' state was detected monitors USB bus status (logic 1 = suspend); used when interrupt is serviced enables output INT to signal `suspend' state enables SoftConnect pull-up resistor to USB bus a HIGH-to-LOW transition enables `suspend' state selects internal (SoftConnect) or external pull-up resistor enables wake-up on LOW level of input CS selects powered-off mode during `suspend' state sending data AA37H unlocks the internal registers for writing after a `resume' 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 82 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 12. DC DMA transfer Direct Memory Access (DMA) is a method to transfer data from one location to another in a computer system, without intervention of the Central Processor Unit (CPU). Many different implementations of DMA exist. The ISP1161A DC supports two methods: * 8237 compatible mode: based on the DMA subsystem of the IBM personal computers (PC, AT and all its successors and clones); this architecture uses the Intel 8237 DMA controller and has separate address spaces for memory and I/O * DACK-only mode: based on the DMA implementation in some embedded RISC processors, which has a single address space for both memory and I/O. ISP1161A's DC supports DMA transfer for all 14 configurable endpoints (see Table 66). Only one endpoint at a time can be selected for DMA transfer. The DMA operation of ISP1161A's DC can be interleaved with normal I/O mode access to other endpoints. The following features are supported: * Single-cycle or burst transfers (up to 16 bytes per cycle) * Programmable transfer direction (read or write) * Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions, short/empty packet * Programmable signal levels on pins DREQ2 and EOT. 12.1 Selecting an endpoint for DMA transfer The target endpoint for DMA access is selected via bits EPDIX[3:0] in the DcDMAConfiguration Register, as shown in Table 71. The transfer direction (read or write) is automatically set by bit EPDIR in the associated ECR, to match the selected endpoint type (OUT endpoint: read; IN endpoint: write). Asserting input DACK2 automatically selects the endpoint specified in the DcDMAConfiguration Register, regardless of the current endpoint used for I/O mode access. Table 71: Endpoint selection for DMA transfer EPIDX[3:0] 0010 0011 0100 0101 0110 0111 1000 1001 1010 Transfer direction EPDIR = 0 OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read EPDIR = 1 IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Endpoint identifier 1 2 3 4 5 6 7 8 9 9397 750 09568 Product data Rev. 01 -- 02 August 2002 83 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Endpoint selection for DMA transfer...continued EPIDX[3:0] 1011 1100 1101 1110 1111 Transfer direction EPDIR = 0 OUT: read OUT: read OUT: read OUT: read OUT: read EPDIR = 1 IN: write IN: write IN: write IN: write IN: write Table 71: Endpoint identifier 10 11 12 13 14 12.2 8237 compatible mode The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the DcHardwareConfiguration Register (see Table 83). The pin functions for this mode are shown in Table 72. Table 72: Symbol DREQ2 DACK2 EOT RD WR 8237 compatible mode: pin functions Description DC's DMA request DC's DMA acknowledge end of transfer read strobe write strobe I/O O I I I I Function ISP1161A's DC requests a DMA transfer DMA controller confirms the transfer DMA controller terminates the transfer instructs ISP1161A's DC to put data on the bus instructs ISP1161A's DC to get data from the bus The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA controller. It operates as a `fly-by' DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of ISP1161A's DC in 8237 compatible DMA mode is given in Figure 40. The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge). General control signals are HRQ (Hold Request), HLDA (Hold Acknowledge) and EOP (End-Of-Process). The bus operation is controlled via MEMR (Memory Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write). D0 to D15 RAM MEMR MEMW ISP1161A DEVICE CONTROLLER DREQ2 DACK2 RD WR DMA CONTROLLER 8237 DREQ DACK IOR IOW HRQ HLDA CPU HRQ HLDA 004aaa093 Fig 40. ISP1161A's device controller in 8237 compatible DMA mode. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 84 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller The following example shows the steps which occur in a typical DMA transfer: 1. ISP1161A's DC receives a data packet in one of its endpoint FIFOs; the packet must be transferred to memory address 1234H. 2. ISP1161A's DC asserts the DREQ2 signal requesting the 8237 for a DMA transfer. 3. The 8237 asks the CPU to release the bus by asserting the HRQ signal. 4. After completing the current instruction cycle, the CPU places the bus control signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and asserts HLDA to inform the 8237 that it has control of the bus. 5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR control signals. 6. The 8237 asserts DACK to inform ISP1161A's DC that it will start a DMA transfer. 7. ISP1161A's DC now places the word to be transferred on the data bus lines, because its RD signal was asserted by the 8237. 8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This latches and stores the word at the desired memory location. It also informs ISP1161A's DC that the data on the bus lines has been transferred. 9. ISP1161A's DC de-asserts the DREQ2 signal to indicate to the 8237 that DMA is no longer needed. In Single cycle mode this is done after each word, in Burst mode following the last transferred word of the DMA cycle. 10. The 8237 de-asserts the DACK output indicating that ISP1161A's DC must stop placing data on the bus. 11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and de-asserts the HRQ signal, informing the CPU that it has released the bus. 12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the CPU resumes the execution of instructions. For a typical bulk transfer the above process is repeated, once for each byte. After each byte the address register in the DMA controller is incremented and the byte counter is decremented. When using 16-bit DMA the number of transfers is 32, and address incrementing and byte counter decrementing is done by 2 for each word. 12.3 DACK-only mode The DACK-only DMA mode is selected by setting bit DAKOLY in the DcHardwareConfiguration Register (see Table 83). The pin functions for this mode are shown in Table 73. A typical example of ISP1161A's DC in DACK-only DMA mode is given in Figure 41. Table 73: Symbol DREQ2 DACK2 DACK-only mode: pin functions Description DC's DMA request DC's DMA acknowledge I/O O I Function ISP1161A DC requests a DMA transfer DMA controller confirms the transfer; also functions as data strobe 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 85 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller DACK-only mode: pin functions...continued Description End-Of-Transfer read strobe write strobe I/O I I I Function DMA controller terminates the transfer not used not used Table 73: Symbol EOT RD WR In DACK-only mode ISP1161A's DC uses the DACK2 signal as a data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes. ISP1161A DEVICE CONTROLLER DREQ2 DACK2 DMA CONTROLLER DREQ DACK HRQ HLDA RD WR CPU HRQ HLDA D0 to D15 RAM 004aaa094 Fig 41. ISP1161A's device controller in DACK-only DMA mode. 12.4 End-Of-Transfer conditions 12.4.1 Bulk endpoints A DMA transfer to/from a bulk endpoint can be terminated by any of the following conditions (bit names refer to the DcDMAConfiguration Register, see Table 87): * An external End-Of-Transfer signal occurs on input EOT * The DMA transfer completes as programmed in the DcDMACounter Register (CNTREN = 1) * A short packet is received on an enabled OUT endpoint (SHORTP = 1) * DMA operation is disabled by clearing bit DMAEN. External EOT: When reading from an OUT endpoint, an external EOT will stop the DMA operation and clear any remaining data in the current FIFO. For a doublebuffered endpoint the other (inactive) buffer is not affected. When writing to an IN endpoint, an EOT will stop the DMA operation and the data packet in the FIFO (even if it is smaller than the maximum packet size) will be sent to the USB host at the next IN token. DcDMACounter Register: An EOT from the DcDMACounter Register is enabled by setting bit CNTREN in the DcDMAConfiguration Register. The ISP1161A has a 16-bit DcDMACounter Register, which specifies the number of bytes to be transferred. When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 86 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller value from the DcDMACounter Register. When the internal counter completes the transfer as programmed in the DcDMACounter, an EOT condition is generated and the DMA operation stops. Short packet: Normally, the transfer byte count must be set via a control endpoint before any DMA transfer takes place. When a short packet has been enabled as EOT indicator (SHORTP = 1), the transfer size is determined by the presence of a short packet in the data. This mechanism permits the use of a fully autonomous data transfer protocol. When reading from an OUT endpoint, reception of a short packet at an OUT token will stop the DMA operation after transferring the data bytes of this packet. Table 74: EOT input DcDMACounter Register Summary of EOT conditions for a bulk endpoint OUT endpoint EOT is active transfer completes as programmed in the DcDMACounter register short packet is received and transferred DMAEN = 0[1] IN endpoint EOT is active transfer completes as programmed in the DcDMACounter register counter reaches zero in the middle of the buffer DMAEN = 0[1] EOT condition Short packet DMAEN bit in DcDMAConfiguration Register [1] The DMA transfer stops. However, no interrupt is generated. 12.4.2 Isochronous endpoints A DMA transfer to/from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the DcDMAConfiguration Register, see Table 87): * An external End-Of-Transfer signal occurs on input EOT * The DMA transfer completes as programmed in the DcDMACounter Register (CNTREN = 1) * An End-Of-Packet (EOP) signal is detected * DMA operation is disabled by clearing bit DMAEN. Table 75: Recommended EOT usage for isochronous endpoints OUT endpoint do not use do not use preferred IN endpoint preferred preferred do not use EOT condition EOT input active DMA Counter Register zero End-Of-Packet 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 87 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 13. DC commands and registers The functions and registers of ISP1161A's DC are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands and registers is given in Table 76. A complete access consists of two phases: 1. Command phase: when address bit A0 = 1, the DC interprets the data on the lower byte of the bus (bits D7 to D0) as a command code. Commands without a data phase are executed immediately. 2. Data phase (optional): when address bit A0 = 0, the DC transfers the data on the bus to or from a register or endpoint FIFO. Multi-byte registers are accessed least significant byte/word first. As the ISP1161A DC's data bus is 16 bits wide: * The upper byte (bits D15 to D8) in command phase, or the undefined byte in data phase and is ignored. * The access of registers is word-aligned: byte access is not allowed. * If the packet length is odd, the upper byte of the last word in an IN endpoint buffer is not transmitted to the host. When reading from an OUT endpoint buffer, the upper byte of the last word must be ignored by the firmware. The packet length is stored in the first 2 bytes of the endpoint buffer. Table 76: Name Initialization commands Write Control OUT Configuration Write Control IN Configuration Write Endpoint n Configuration (n = 1 to 14) Read Control OUT Configuration Read Control IN Configuration Read Endpoint n Configuration (n = 1 to 14) Write/Read Device Address Write/Read Mode Register Write/Read DcHardwareConfiguration Write/Read Interrupt Enable Register Write/Read DMA Configuration Write/Read DMA Counter Reset Device 9397 750 09568 DC command and register summary Destination DcEndpointConfiguration Register endpoint 0 OUT DcEndpointConfiguration Register endpoint 0 IN DcEndpointConfiguration Register endpoint 1 to 14 DcEndpointConfiguration Register endpoint 0 OUT DcEndpointConfiguration Register endpoint 0 IN DcEndpointConfiguration Register endpoint 1 to 14 DcAddress Register DcMode Register DcHardwareConfiguration Register DcInterruptEnable Register DcDMAConfiguration Register DcDMACounter Register resets all registers Code (Hex) 20 21 22 to 2F 30 31 32 to 3F B6/B7 B8/B9 BA/BB C2/C3 F0/F1 F2/F3 F6 Transaction[1] write 1 word write 1 word write 1 word read 1 word read 1 word read 1 word write/read 1 word write/read 1 word write/read 1 word write/read 2 words write/read 1 word write/read 1 word (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 88 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 76: Name DC command and register summary...continued Destination illegal: endpoint is read-only FIFO endpoint 0 IN FIFO endpoint 1 to 14 (IN endpoints only) FIFO endpoint 0 OUT illegal: endpoint is write-only FIFO endpoint 1 to 14 (OUT endpoints only) Endpoint 0 OUT Endpoint 0 IN Endpoint 1 to 14 DcEndpointStatus Register endpoint 0 OUT DcEndpointStatus Register endpoint 0 IN DcEndpointStatus Register n endpoint 1 to 14 illegal: IN endpoints only[2] FIFO endpoint 0 IN[2] FIFO endpoint 1 to 14 (IN endpoints only)[2] FIFO endpoint 0 OUT illegal[3] FIFO endpoint 1 to 14 (OUT endpoints only)[3] Endpoint 0 OUT Endpoint 0 IN Endpoint 1 to 14 DcEndpointStatusImage Register endpoint 0 OUT DcEndpointStatusImage Register endpoint 0 IN DcEndpointStatusImage Register n endpoint 1 to 14 Endpoint 0 IN and OUT DcErrorCode Register endpoint 0 OUT DcErrorCode Register endpoint 0 IN Code (Hex) (00) 01 02 to 0F 10 (11) 12 to 1F Transaction[1] N 64 bytes isochronous: N 1023 bytes interrupt/bulk: N 64 bytes N 64 bytes isochronous: N 1023 bytes[6] interrupt/bulk: N 64 bytes read 1 word read 1 word read 1 word none none none none read 1 word read 1 word read 1 word none read 1 word [5] read 1 word [5] Data flow commands Write Control OUT Buffer Write Control IN Buffer Write Endpoint n Buffer (n = 1 to 14) Read Control OUT Buffer Read Control IN Buffer Read Endpoint n Buffer (n = 1 to 14) Stall Control OUT Endpoint Stall Control IN Endpoint Stall Endpoint n (n = 1 to 14) Read Control OUT Status Read Control IN Status Read Endpoint n Status (n = 1 to 14) Validate Control OUT Buffer Validate Control IN Buffer Validate Endpoint n Buffer (n = 1 to 14) Clear Control OUT Buffer Clear Control IN Buffer Clear Endpoint n Buffer (n = 1 to 14) Unstall Control OUT Endpoint Unstall Control IN Endpoint Unstall Endpoint n (n = 1 to 14) Check Control OUT Status[4] Check Control IN Status[4] Check Endpoint n Status (n = 1 to 14)[4] Acknowledge Setup General commands Read Control OUT Error Code Read Control IN Error Code A0 A1 40 41 42 to 4F 50 51 52 to 5F (60) 61 62 to 6F 70 (71) 72 to 7F 80 81 82 to 8F D0 D1 D2 to DF F4 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 89 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 76: Name DC command and register summary...continued Destination DcErrorCode Register endpoint 1 to 14 all registers with write access DcScratch Register DcFrameNumber Register DcChipID Register DcInterrupt Register Code (Hex) A2 to AF B0 B2/B3 B4 B5 C0 Transaction[1] read 1 word [5] write 1 word write/read 1 word read 1 word read 1 word read 2 words Read Endpoint n Error Code (n = 1 to 14) Unlock Device Write/Read Scratch Register Read frame Number Read Chip ID Read Interrupt Register [1] [2] [3] [4] [5] [6] With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2. Validating an OUT endpoint buffer causes unpredictable behavior of ISP1161A's DC. Clearing an IN endpoint buffer causes unpredictable behavior of ISP1161A's DC. Reads a copy of the Status Register: executing this command does not clear any status bits or interrupt bits. When accessing an 8-bit register in 16-bit mode, the upper byte is invalid. During isochronous transfer in 16-bit mode, because N 1023, the firmware must take care of the upper byte. 13.1 Initialization commands Initialization commands are used during the enumeration process of the USB network. These commands are used to configure and enable the embedded endpoints. They also serve to set the USB assigned address of ISP1161A's DC and to perform a device reset. 13.1.1 DcEndpointConfiguration Register (R/W: 30H-3FH/20H-2FH) This command is used to access the Endpoint Configuration Register (ECR) of the target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction (OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The register bit allocation is shown in Table 77. A bus reset will disable all endpoints. The allocation of FIFO memory only takes place after all 16 endpoints have been configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control endpoints have fixed configurations, they must be included in the initialization sequence and be configured with their default values (see Table 66). Automatic FIFO allocation starts when endpoint 14 has been configured. Remark: If any change is made to an endpoint configuration which affects the allocated memory (size, enable/disable), the FIFO memory contents of all endpoints becomes invalid. Therefore, all valid data must be removed from enabled endpoints before changing the configuration. Code (Hex): 20 to 2F -- write (control OUT, control IN, endpoint 1 to 14) Code (Hex): 30 to 3F -- read (control OUT, control IN, endpoint 1 to 14) Transaction -- write/read 1 word Table 77: Bit Symbol Reset Access 9397 750 09568 DcEndpointConfiguration Register: bit allocation 7 FIFOEN 0 R/W 6 EPDIR 0 R/W 5 DBLBUF 0 R/W 4 FFOISO 0 R/W 0 R/W 0 R/W 3 2 FFOSZ[3:0] 0 R/W 0 R/W 1 0 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 90 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller DcEndpointConfiguration Register: bit description Symbol FIFOEN EPDIR DBLBUF FFOISO FFOSZ[3:0] Description A logic 1 indicates an enabled FIFO with allocated memory. A logic 0 indicates a disabled FIFO (no bytes allocated). This bit defines the endpoint direction (0 = OUT, 1 = IN); it also determines the DMA transfer direction (0 = read, 1 = write). A logic 1 indicates that this endpoint has double buffering. A logic 1 indicates an isochronous endpoint. A logic 0 indicates a bulk or interrupt endpoint. Selects the FIFO size according to Table 67 Table 78: Bit 7 6 5 4 3 to 0 13.1.2 DcAddress Register (R/W: B7H/B6H) This command is used to set the USB assigned address in the DcAddress Register and enable the USB device. The DcAddress Register bit allocation is shown in Table 79. A USB bus reset sets the device address to 00H (internally) and enables the device. The value of the DcAddress Register (accessible by the microcontroller) is not altered by the bus reset. In response to the standard USB request, Set Address, the firmware must issue a Write Device Address command, followed by sending an empty packet to the host. The new device address is activated when the host acknowledges the empty packet. Code (Hex): B6/B7 -- write/read Address Register Transaction -- write/read 1 word Table 79: Bit Symbol Reset Access DcAddress Register: bit allocation 7 DEVEN 0 R/W 0 R/W Table 80: Bit 7 6 to 0 0 R/W 0 R/W 6 5 4 3 DEVADR[6:0] 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0 DcAddress Register: bit description Symbol DEVEN DEVADR[6:0] Description A logic 1 enables the device. This field specifies the USB device address. 13.1.3 DcMode Register (R/W: B9H/B8H) This command is used to access the ISP1161A's DcMode Register, which consists of 1 byte (for bit allocation: see Table 80). In 16-bit bus mode the upper byte is ignored. The DcMode Register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It can be used to enable debug mode, where all errors and Not Acknowledge (NAK) conditions will generate an interrupt. Code (Hex): B8/B9 -- write/read Mode Register Transaction -- write/read 1 word 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 91 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 81: Bit Symbol Reset Access [1] DcMode Register: bit allocation 7 DMAWD 0[1] R/W 6 reserved 0 R/W 5 GOSUSP 0 R/W 4 reserved 0 R/W 3 INTENA 0[1] R/W 2 DBGMOD 0[1] R/W 1 reserved 0[1] R/W 0 SOFTCT 0[1] R/W Unchanged by a bus reset. Table 82: Bit 7 DcMode Register: bit description Symbol DMAWD Description A logic 1 selects 16-bit DMA bus width (bus configuration modes 0 and 2). A logic 0 selects 8-bit DMA bus width. Bus reset value: unchanged. reserved Writing a logic 1 followed by a logic 0 will activate `suspend' mode. reserved A logic 1 enables all DC interrupts. Bus reset value: unchanged. A logic 1 enables debug mode. where all NAKs and errors will generate an interrupt. A logic 0 selects normal operation, where interrupts are generated on every ACK (bulk endpoints) or after every data transfer (isochronous endpoints). Bus reset value: unchanged. reserved A logic 1 enables SoftConnect (see Section 7.5). This bit is ignored if EXTPUL = 1 in the DcHardwareConfiguration Register (see Table 83). Bus reset value: unchanged. 6 5 4 3 2 GOSUSP INTENA DBGMOD 1 0 SOFTCT 13.1.4 DcHardwareConfiguration Register (R/W: BBH/BAH) This command is used to access the DcHardwareConfiguration Register, which consists of 2 bytes. The first (lower) byte contains the device configuration and control values, the second (upper) byte holds the clock control bits and the clock division factor. The bit allocation is given in Table 83. A bus reset will not change any of the programmed bit values. The DcHardwareConfiguration Register controls the connection to the USB bus, clock activity and power supply during `suspend' state, output clock frequency, DMA operating mode and pin configurations (polarity, signalling mode). Code (Hex): BA/BB -- write/read DcHardwareConfiguration Register Transaction -- write/read 1 word Table 83: Bit Symbol Reset Access DcHardwareConfiguration Register: bit allocation 15 reserved 0 R/W 14 EXTPUL 0 R/W 13 NOLAZY 1 R/W 12 CLKRUN 0 R/W 0 R/W 0 R/W 11 10 CKDIV[3:0] 1 R/W 1 R/W 9 8 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 92 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 5 DAKPOL 0 R/W 4 EOTPOL 0 R/W 3 WKUPCS 0 R/W 2 PWROFF 0 R/W 1 INTLVL 0 R/W 0 INTPOL 0 R/W Bit Symbol Reset Access 7 DAKOLY 0 R/W 6 DRQPOL 1 R/W Table 84: Bit 15 14 DcHardwareConfiguration Register: bit description Symbol EXTPUL Description reserved A logic 1 indicates that an external 1.5 k pull-up resistor is used on pin D+ and that SoftConnect is not used. Bus reset value: unchanged. A logic 1 disables output on pin CLKOUT of the LazyClock frequency (100 50% kHz) during `suspend' state. A logic 0 causes pin CLKOUT to switch to LazyClock output after approximately 2 ms delay, following the setting of bit GOSUSP in the DcMode Register. Bus reset value: unchanged. A logic 1 indicates that the internal clocks are always running, even during `suspend' state. A logic 0 switches off the internal oscillator and PLL, when they are not needed. During `suspend' state this bit must be made logic 0 to meet the suspend current requirements. The clock is stopped after a delay of approximately 2 ms, following the setting of bit GOSUSP in the DcMode Register. Bus reset value: unchanged. This field specifies the clock division factor N, which controls the clock frequency on output CLKOUT. The output frequency in MHz is given by 48 / (N + 1). The clock frequency range is 3 to 48 MHz (N = 0 to 15). with a reset value of 12 MHz (N = 3). The hardware design guarantees no glitches during frequency change. Bus reset value: unchanged. A logic 1 selects DACK-only DMA mode. A logic 0 selects 8237 compatible DMA mode. Bus reset value: unchanged. Selects DREQ2 pin signal polarity (0 = active LOW, 1 = active HIGH). Bus reset value: unchanged. Selects DACK2 pin signal polarity (0 = active LOW). Bus reset value: unchanged. Selects EOT pin signal polarity (0 = active LOW, 1 = active HIGH). Bus reset value: unchanged. A logic 1 enables remote wake-up via a LOW level on input pin CS (VBUS must be present for wake-up on CS). Bus reset value: unchanged. A logic 1 enables powering-off during `suspend' state. Output D_SUSPEND pin is configured as a power switch control signal for external devices (HIGH during `suspend'). This value should always be initialized to logic 1. Bus reset value: unchanged. Selects the interrupt signalling mode on output pin INT2 (0 = level, 1 = pulsed). In pulsed mode an interrupt produces an 166 ns pulse. See Section 8.6.3 for details. Bus reset value: unchanged. Selects INT2 pin signal polarity (0 = active LOW, 1 = active HIGH). Bus reset value: unchanged. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 13 NOLAZY 12 CLKRUN 11 to 8 CKDIV[3:0] 7 6 5 4 3 DAKOLY DRQPOL DAKPOL EOTPOL WKUPCS 2 PWROFF 1 INTLVL 0 INTPOL 9397 750 09568 Product data Rev. 01 -- 02 August 2002 93 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 13.1.5 DcInterruptEnable Register (R/W: C3H/C2H) This command is used to individually enable/disable interrupts from all endpoints, as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend, resume, reset). A bus reset will not change any of the programmed bit values. The command accesses the Interrupt Enable Register, which consists of 4 bytes. The bit allocation is given in Table 85. Code (Hex): C2/C3 -- write/read Interrupt Enable Register Transaction -- write/read 2 words Table 85: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Interrupt Enable Register: bit allocation 31 30 29 28 reserved 00H R/W 23 IEP14 0 R/W 15 IEP6 0 R/W 7 reserved 0 R/W 22 IEP13 0 R/W 14 IEP5 0 R/W 6 SP_IEEOT 0 R/W Table 86: Bit 31 to 24 23 to 10 9 8 7 6 5 4 3 2 1 0 21 IEP12 0 R/W 13 IEP4 0 R/W 5 IEPSOF 0 R/W 20 IEP11 0 R/W 12 IEP3 0 R/W 4 IESOF 0 R/W 19 IEP10 0 R/W 11 IEP2 0 R/W 3 IEEOT 0 R/W 18 IEP9 0 R/W 10 IEP1 0 R/W 2 IESUSP 0 R/W 17 IEP8 0 R/W 9 IEP0IN 0 R/W 1 IERESM 0 R/W 16 IEP7 0 R/W 8 IEP0OUT 0 R/W 0 IERST 0 R/W 27 26 25 24 Interrupt Enable Register: bit description Symbol IEP0IN IEP0OUT SP_IEEOT IEPSOF IESOF IEEOT IESUSP IERESM IERST Description reserved; must write logic 0 A logic 1 enables interrupts from the control IN endpoint. A logic 1 enables interrupts from the control OUT endpoint. reserved A logic 1 enables interrupt upon detection of a short packet. A logic 1 enables 1 ms interrupts upon detection of Pseudo SOF. A logic 1 enables interrupt upon SOF detection. A logic 1 enables interrupt upon EOT detection. A logic 1 enables interrupt upon detection of `suspend' state. A logic 1 enables interrupt upon detection of a `resume' state. A logic 1 enables interrupt upon detection of a bus reset. IEP14 to IEP1 A logic 1 enables interrupts from the indicated endpoint. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 94 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 13.1.6 DcDMAConfiguration Register (R/W: F1H/F0H) This command defines the DMA configuration of ISP1161A's DC and enables/disables DMA transfers. The command accesses the DcDMAConfiguration Register, which consists of 2 bytes. The bit allocation is given in Table 87. A bus reset will clear bit DMAEN (DMA disabled), all other bits remain unchanged. Code (Hex): F0/F1 -- write/read DMA Configuration Transaction -- write/read 1 word Table 87: Bit Symbol Reset Access Bit Symbol Reset Access [1] DcDMAConfiguration Register: bit allocation 15 CNTREN 0[1] R/W 7 0[1] R/W 14 SHORTP 0[1] R/W 6 EPDIX[3:0] 0[1] R/W 0[1] R/W 0[1] R/W 13 reserved 0[1] R/W 5 12 reserved 0[1] R/W 4 11 reserved 0[1] R/W 3 DMAEN 0 R/W 10 reserved 0[1] R/W 2 reserved 0 R/W 9 reserved 0[1] R/W 1 0[1] R/W 8 reserved 0[1] R/W 0 0[1] R/W BURSTL[1:0] Unchanged by a bus reset. Table 88: Bit 15 DcDMAConfiguration Register: bit description Symbol CNTREN Description A logic 1 enables the generation of an EOT condition, when the DMA Counter Register reaches zero. Bus reset value: unchanged. A logic 1 enables short/empty packet mode. When receiving (OUT endpoint) a short/empty packet an EOT condition is generated. When transmitting (IN endpoint), this bit should be cleared. Bus reset value: unchanged. reserved Indicates the destination endpoint for DMA, see Table 71. Writing a logic 1 enables DMA transfer, a logic 0 forces the end of an ongoing DMA transfer. Reading this bit indicates whether DMA is enabled (0 = DMA stopped, 1 = DMA enabled). This bit is cleared by a bus reset. reserved Selects the DMA burst length: 00 -- single-cycle mode (1 byte) 01 -- burst mode (4 bytes) 10 -- burst mode (8 bytes) 11 -- burst mode (16 bytes). Bus reset value: unchanged. 14 SHORTP 13 to 8 7 to 4 3 EPDIX[3:0] DMAEN 2 1 to 0 BURSTL[1:0] For selecting an endpoint for device DMA transfer, see Section 11.2. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 95 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 13.1.7 DcDMACounter Register (R/W: F3H/F2H) This command accesses the DcDMACounter Register. The bit allocation is given in Table 89. Writing to the register sets the number of bytes for a DMA transfer. Reading the register returns the number of remaining bytes in the current transfer. A bus reset will not change the programmed bit values. The internal DMA counter is automatically reloaded from the DcDMACounter Register when DMA is re-enabled (DMAEN = 1). See Section 13.1.6 for more details. Code (Hex): F2/F3 -- write/read DcDMACounter Register Transaction -- write/read 1 word Table 89: Bit Symbol Reset Access Bit Symbol Reset Access DcDMACounter Register: bit allocation 15 14 13 12 00H R/W 7 6 5 4 00H R/W Table 90: Bit 15 to 0 DcDMACounter Register: bit description Symbol DMACR[15:0] Description DMA Counter Register 3 2 1 0 DMACR[7:0] 11 10 9 8 DMACR[15:8] 13.1.8 Reset Device (F6H) This command resets the ISP1161A DC in the same way as an external hardware reset via input RESET. All registers are initialized to their `reset' values. Code (Hex): F6 -- reset the device Transaction -- none 13.2 Data flow commands Data flow commands are used to manage the data transmission between the USB endpoints and the system microprocessor. Much of the data flow is initiated via an interrupt to the microprocessor. The data flow commands are used to access the endpoints and determine whether the endpoint FIFOs contain valid data. Remark: The IN buffer of an endpoint contains input data for the host, the OUT buffer receives output data from the host. 13.2.1 Write/Read Endpoint Buffer (R/W: 10H,12H-1FH/01H-0FH) This command is used to access endpoint FIFO buffers for reading or writing. First, the buffer pointer is reset to the beginning of the buffer. Following the command, a maximum of (M + 1) words can be written or read, with M given by (N + 1) DIV 2, N representing the size of the endpoint buffer. After each read/write action the buffer pointer is automatically incremented by 2. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 96 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller In DMA access, the first word (the packet length) is skipped: transfers start at the second word of the endpoint buffer. When reading, the ISP1161A DC can detect the last word via the End of Packet (EOP) condition. When writing to a bulk/interrupt endpoint, the endpoint buffer must be completely filled before sending the data to the host. Exception: when a DMA transfer is stopped by an external EOT condition, the current buffer content (full or not) is sent to the host. Remark: Reading data after a Write Endpoint Buffer command or writing data after a Read Endpoint Buffer command will cause unpredictable behavior of the ISP1161A DC. Code (Hex): 01 to 0F -- write (control IN, endpoint 1 to 14) Code (Hex): 10, 12 to 1F -- read (control OUT, endpoint 1 to 14) Transaction -- write/read maximum (M + 1) words (isochronous endpoint: N 1023, bulk/interrupt endpoint: N 32) The data in the endpoint FIFO must be organized as shown in Table 91. An example of endpoint FIFO access is given Table 92. Table 91: Word # 0 (lower byte) 0 (upper byte) 1 (lower byte) 1 (upper byte) ... M = (N + 1) DIV 2 Table 92: A0 1 0 0 0 ... Endpoint FIFO organization Description packet length (lower byte) packet length (upper byte) data byte 1 data byte 2 ... data byte N Example of endpoint FIFO access Phase command data data data ... Bus lines D[7:0] D[15:8] D[15:0] D[15:0] D[15:0] ... Word # 0 1 2 ... Description command code (00H to 1FH) ignored packet length data word 1 (data byte 2, data byte 1) data word 2 (data byte 4, data byte 3) ... Remark: There is no protection against writing or reading past a buffer's boundary or against writing into an OUT buffer or reading from an IN buffer. Any of these actions could cause an incorrect operation. Data residing in an OUT buffer are only meaningful after a successful transaction. Exception: during DMA access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 97 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 13.2.2 DcEndpointStatus Register (R: 50H-5FH) This command is used to read the status of an endpoint FIFO. The command accesses the DcEndpointStatus Register, the bit allocation of which is shown in Table 93. Reading the DcEndpointStatus Register will clear the interrupt bit set for the corresponding endpoint in the DcInterrupt Register (see Table 109). All bits of the DcEndpointStatus Register are read-only. Bit EPSTAL is controlled by the Stall/Unstall commands and by the reception of a SETUP token (see Section 13.2.3). Code (Hex): 50 to 5F -- read (control OUT, control IN, endpoint 1 to 14) Transaction -- read 1 word Table 93: Bit Symbol Reset Access DcEndpointStatus Register: bit allocation 7 EPSTAL 0 R 6 EPFULL1 0 R Table 94: Bit 7 5 EPFULL0 0 R 4 DATA_PID 0 R 3 OVER WRITE 0 R 2 SETUPT 0 R 1 CPUBUF 0 R 0 reserved 0 R DcEndpointStatus Register: bit description Symbol EPSTAL Description This bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by an Unstall Endpoint command. The endpoint is automatically unstalled upon reception of a SETUP token. 6 5 4 3 EPFULL1 EPFULL0 DATA_PID OVERWRITE A logic 1 indicates that the secondary endpoint buffer is full. A logic 1 indicates that the primary endpoint buffer is full. This bit indicates the data PID of the next packet (0 = DATA PID, 1 = DATA1 PID). This bit is set by hardware, a logic 1 indicating that a new Setup packet has overwritten the previous set-up information, before it was acknowledged or before the endpoint was stalled. If writing the set-up data has finished, this bit is cleared by a read action. Firmware must check this bit before sending an Acknowledge Setup command or stalling the endpoint. Upon reading a logic 1, the firmware must stop ongoing setup actions and wait for a new Setup packet. 2 1 0 SETUPT CPUBUF - A logic 1 indicates that the buffer contains a Setup packet. This bit indicates which buffer is currently selected for CPU access (0 = primary buffer, 1 = secondary buffer). reserved 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 98 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 13.2.3 Stall Endpoint/Unstall Endpoint (40H-4FH/80H-8FH) These commands are used to stall or unstall an endpoint. The commands modify the content of the DcEndpointStatus Register (see Table 93). A stalled control endpoint is automatically unstalled when it receives a SETUP token, regardless of the packet content. If the endpoint should stay in its stalled state, the microprocessor can re-stall it with the Stall Endpoint command. When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by receiving a SETUP token), it is also re-initialized. This flushes the buffer: if it is an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID. Code (Hex): 40 to 4F -- stall (control OUT, control IN, endpoint 1 to 14) Code (Hex): 80 to 8F -- unstall (control OUT, control IN, endpoint 1 to 14) Transaction -- none 13.2.4 Validate Endpoint Buffer (R/W: 6FH/61H) This command signals the presence of valid data for transmission to the USB host, by setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in the buffer is valid and can be sent to the host, when the next IN token is received. For a double-buffered endpoint this command switches the current FIFO for CPU access. Remark: For special aspects of the control IN endpoint see Section 11.3.6. Code (Hex): 61 to 6F -- validate endpoint buffer (control IN, endpoint 1 to 14) Transaction -- none 13.2.5 Clear Endpoint Buffer (70H, 72H-7FH) This command unlocks and clears the buffer of the selected OUT endpoint, allowing the reception of new packets. Reception of a complete packet causes the Buffer Full flag of an OUT endpoint to be set. Any subsequent packets are refused by returning a NAK condition, until the buffer is unlocked using this command. For a double-buffered endpoint this command switches the current FIFO for CPU access. Remark: For special aspects of the control OUT endpoint see Section 11.3.6. Code (Hex): 70, 72 to 7F -- clear endpoint buffer (control OUT, endpoint 1 to 14) Transaction -- none 13.2.6 DcEndpointStatusImage Register(D0H-DFH) This command is used to check the status of the selected endpoint FIFO without clearing any status or interrupt bits. The command accesses the DcEndpointStatusImage Register, which contains a copy of the DcEndpointStatus Register. The bit allocation of the DcEndpointStatusImage Register is shown in Table 95. Code (Hex): D0 to DF -- check status (control OUT, control IN, endpoint 1 to 14) Transaction -- write/read 1 word 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 99 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 95: Bit Symbol Reset Access DcEndpointStatusImage Register: bit allocation 7 EPSTAL 0 R 6 EPFULL1 0 R Table 96: Bit 7 6 5 4 3 5 EPFULL0 0 R 4 DATA_PID 0 R 3 OVER WRITE 0 R 2 SETUPT 0 R 1 CPUBUF 0 R 0 reserved 0 R DcEndpointStatusImage Register: bit description Symbol EPSTAL EPFULL1 EPFULL0 DATA_PID OVERWRITE Description This bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). A logic 1 indicates that the secondary endpoint buffer is full. A logic 1 indicates that the primary endpoint buffer is full. This bit indicates the data PID of the next packet (0 = DATA PID, 1 = DATA1 PID). This bit is set by hardware, a logic 1 indicating that a new Setup packet has overwritten the previous set-up information, before it was acknowledged or before the endpoint was stalled. If writing the set-up data has finished, this bit is cleared by a read action. Firmware must check this bit before sending an Acknowledge Setup command or stalling the endpoint. Upon reading a logic 1 the firmware must stop ongoing set-up actions and wait for a new Setup packet. 2 1 0 SETUPT CPUBUF - A logic 1 indicates that the buffer contains a Setup packet. This bit indicates which buffer is currently selected for CPU access (0 = primary buffer, 1 = secondary buffer). reserved 13.2.7 Acknowledge Setup (F4H) This command acknowledges to the host that a SETUP packet was received. The arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The microprocessor needs to re-enable these commands by sending an Acknowledge Setup command, see Section 11.3.6. Code (Hex): F4 -- acknowledge setup Transaction -- none 13.3 General commands 13.3.1 Read Endpoint Error Code (R: A0H-AFH) This command returns the status of the last transaction of the selected endpoint, as stored in the DcErrorCode Register. Each new transaction overwrites the previous status information. The bit allocation of the DcErrorCode Register is shown in Table 97. Code (Hex): A0 to AF -- read error code (control OUT, control IN, endpoint 1 to 14) Transaction -- read 1 word 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 100 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 97: Bit Symbol Reset Access DcErrorCode Register: bit allocation 7 UNREAD 0 R 6 DATA01 0 R Table 98: Bit 7 6 5 4 to 1 0 5 reserved 0 R 0 R 0 R 4 3 ERROR[3:0] 0 R 0 R 2 1 0 RTOK 0 R DcErrorCode Register: bit description Symbol UNREAD DATA01 ERROR[3:0] RTOK Description A logic 1 indicates that a new event occurred before the previous status was read. This bit indicates the PID type of the last successfully received or transmitted packet (0 = DATA0 PID, 1 = DATA1 PID). reserved Error code. For error description, see Table 99. A logic 1 indicates that data was received or transmitted successfully. Table 99: Error code (Binary) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Transaction error codes Description no error PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0 PID unknown; encoding is valid, but PID does not exist unexpected packet; packet is not of the expected type (token, data, or acknowledge), or is a SETUP token to a non-control endpoint token CRC error data CRC error time-out error babble error unexpected end-of-packet sent or received NAK (Not AcKnowledge) sent Stall; a token was received, but the endpoint was stalled overflow; the received packet was larger than the available buffer space sent empty packet (ISO only) bit stuffing error sync error wrong (unexpected) toggle bit in DATA PID; data was ignored 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 101 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 13.3.2 Unlock Device (B0H) This command unlocks ISP1161A's DC from write-protection mode after a `resume'. In `suspend' state all registers and FIFOs are write-protected to prevent data corruption by external devices during a `resume'. Also, the register access for reading is possible only after the `Unlock Device' command is executed. After waking up from `suspend' state, the firmware must unlock the registers and FIFOs via this command, by writing the unlock code (AA37H) into the Lock Register. The bit allocation of the Lock Register is given in Table 100. Code (Hex): B0 -- unlock the device Transaction -- write 1 word (unlock code) Table 100: Lock Register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access 7 6 5 4 37H W Table 101: Lock Register: bit description Bit 15 to 0 Symbol UNLOCK[15:0] Description Sending data AA37H unlocks the internal registers and FIFOs for writing, following a `resume'. 15 14 13 12 AAH W 3 2 1 0 UNLOCKL[7:0] 11 10 9 8 UNLOCKH[7:0] 13.3.3 DcScratch Register (R/W: B3H/B2H) This command accesses the 16-bit DcScratch Register, which can be used by the firmware to save and restore information, e.g., the device status before powering down in `suspend' state. The register bit allocation is given in Table 102. Code (Hex): B2/B3 -- write/read Scratch Register Transaction -- write/read 1 word Table 102: DcScratch Register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 7 15 14 reserved 0 R/W 6 0 R/W 5 0 R/W 4 SFIRL[7:0] 00H R/W 0 R/W 3 13 12 11 10 SFIRH[4:0] 0 R/W 2 0 R/W 1 0 R/W 0 9 8 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 102 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 103: DcScratch Register: bit description Bit 15 to 13 12 to 0 Symbol SFIR[12:0] Description reserved; must be logic 0 Scratch Information Register 13.3.4 Read Frame Number (R: B4H) This command returns the frame number of the last successfully received SOF. It is followed by reading one word from the DcFrameNumber Register, containing the frame number. The DcFrameNumber Register is shown in Table 104. Remark: After a bus reset, the value of the DcFrameNumber Register is undefined. Code (Hex): B4 -- read frame number Transaction -- read 1 word Table 104: DcFrameNumber Register: bit allocation Bit Symbol Reset[1] Access Bit Symbol Reset[1] Access [1] 15 0 R 7 0 R 14 0 R 6 0 R 13 reserved 0 R 5 0 R 12 0 R 4 11 0 R 3 10 0 R 2 0 R 9 SOFRH[2:0] 0 R 1 0 R 8 0 R 0 0 R SOFRL[7:0] 0 R 0 R Reset value undefined after a bus reset. Table 105: DcFrameNumber Register: bits description Bit 15 to 11 10 to 8 7 to 0 Symbol Description reserved SOFRH[2:0] SOF frame number (upper byte) SOFRL[7:0] SOF frame number (lower byte) Table 106: Example of DcFrameNumber Register access A0 1 0 Phase command data Bus lines D[7:0] D[15:8] D[15:0] Word # 0 Description command code (B4H) ignored frame number 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 103 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 13.3.5 Read Chip ID (R: B5H) This command reads the chip identification code and hardware version number. The firmware must check this information to determine the supported functions and features. This command accesses the DcChipID Register, which is shown in Table 107. Code (Hex): B5 -- read chip ID Transaction -- read 1 word Table 107: DcChipID Register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access 7 6 5 4 XXH R Table 108: DcChipID Register: bit description Bit 15 to 8 7 to 0 Symbol CHIPIDH[7:0] CHIPIDL[7:0] Description chip ID code (61H) silicon version (XXH, with XX representing the BCD encoded version number) 15 14 13 12 61H R 3 2 1 0 CHIPIDL[7:0] 11 10 9 8 CHIPIDH[7:0] 13.3.6 Read Interrupt Register (R: C0H) This command indicates the sources of interrupts as stored in the 4-byte DcInterrupt Register. Each individual endpoint has its own interrupt bit. The bit allocation of the DcInterrupt Register is shown in Table 109. Bit BUSTATUS is used to verify the current bus status in the interrupt service routine. Interrupts are enabled via the Interrupt Enable Register, see Section 13.1.5. Remark: While reading the DcInterrupt Register, it is recommended that both 2 byte words are read completely. Code (Hex): C0 -- read interrupt register Transaction -- read 2 words Table 109: DcInterrupt Register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access 23 EP14 0 R 22 EP13 0 R 21 EP12 0 R 20 EP11 0 R 31 30 29 28 reserved 00H R 19 EP10 0 R 18 EP9 0 R 17 EP8 0 R 16 EP7 0 R 27 26 25 24 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 104 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 13 EP4 0 R 5 PSOF 0 R 12 EP3 0 R 4 SOF 0 R 11 EP2 0 R 3 EOT 0 R 10 EP1 0 R 2 SUSPND 0 R 9 EP0IN 0 R 1 RESUME 0 R 8 EP0OUT 0 R 0 RESET 0 R Bit Symbol Reset Access Bit Symbol Reset Access 15 EP6 0 R 7 BUSTATUS 0 R 14 EP5 0 R 6 SP_EOT 0 R Table 110: DcInterrupt Register: bit description Bit 31 to 24 23 to 10 9 8 7 6 5 Symbol EP14 to EP1 EP0IN EP0OUT BUSTATUS SP_EOT PSOF Description reserved A logic 1 indicates the interrupt source(s): endpoint 14 to 1. A logic 1 indicates the interrupt source: control IN endpoint. A logic 1 indicates the interrupt source: control OUT endpoint. Monitors the current USB bus status (0 = awake, 1 = suspend). A logic 1 indicates that an EOT interrupt has occurred for a short packet. A logic 1 indicates that an interrupt is issued every 1 ms because of the Pseudo SOF; after 3 missed SOFs `suspend' state is entered. A logic 1 indicates that a SOF condition was detected. A logic 1 indicates that an internal EOT condition was generated by the DMA Counter reaching zero. A logic 1 indicates that an `awake' to `suspend' change of state was detected on the USB bus. A logic 1 indicates that a `resume' state was detected. A logic 1 indicates that a bus reset condition was detected. 4 3 2 1 0 SOF EOT SUSPND RESUME RESET 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 105 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 14. Reset Pin RESET is the hardware reset input of ISP1161A. It is active LOW. To reset all internal logic, the minimum timing requirement is 200 ns. VCC ISP1161A reset from microprocessor or pulled HIGH RESET 004aaa095 Fig 42. RESET pin usage. 15. Power supply ISP1161A can operate at either +5 V or +3.3 V. When using +5 V as ISP1161A's power supply input, only VCC (pin 56) can be connected to the +5 V power supply. An application with a +5 V power supply input is shown in Figure 43. ISP1161A has an internal DC/DC regulator to provide +3.3 V for its internal core. This internal +3.3 V can also be obtained from Vreg(3.3) (pin 58) to supply the 1.5 k pull-up resistor of the DC side upstream port signal D_DP. The signal D_DP is connected to the standard USB upstream port connector's pin D+. When using +3.3 V as the power supply input, the internal DC/DC regulator will be bypassed. All four power supply pins (VCC, Vreg(3.3), Vhold1 and Vhold2) can be used as power supply input. It is recommended that you connect all four power supply pins to the +3.3 V power supply, as shown in Figure 44. If, however, you have board space (routing area) constraints, you must connect at least the VCC and the Vreg(3.3) to the 3.3 V power supply. For both +3.3 V and 5 V operation, all four power supply pins should be connected to a decoupling capacitor. +3.3 V ISP1161A 1.5 k to USB upstream port connector VCC D_DP Vreg(3.3) Vhold1 Vhold2 GND +5 V 1.5 k to USB upstream port connector ISP1161A VCC D_DP Vreg(3.3) Vhold1 Vhold2 GND 004aaa096 004aaa097 Fig 43. Using a +5 V supply. 9397 750 09568 Fig 44. Using a +3.3 V supply. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 106 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 16. Crystal oscillator and LazyClock The ISP1161A has a crystal oscillator designed for a 6 MHz parallel-resonant crystal (fundamental). A typical circuit is shown in Figure 45. Alternatively, an external clock signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open. See Figure 46. ISP1161A CLKOUT 18 pF XTAL2 6 MHz XTAL1 18 pF 004aaa098 VCC 6 MHz ISP1161A CLKOUT Out OSC n.c. XTAL2 XTAL1 004aaa099 Fig 45. Oscillator circuit with external crystal. Fig 46. Oscillator circuit using external oscillator. The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL. This frequency is used to generate a programmable clock output signal at pin CLKOUT, ranging from 3 to 48 MHz. In `suspend' state the normal CLKOUT signal is not available, because the crystal oscillator and the PLL are switched off to save power. Instead, the CLKOUT signal can be switched to the LazyClock frequency of 100 50% kHz. The oscillator operation and the CLKOUT frequency are controlled via the DcHardwareConfiguration Register, as shown in Figure 47. The following bits are involved: * CLKRUN switches the oscillator on and off * CLKDIV[3:0] is the division factor determining the normal CLKOUT frequency * NOLAZY controls the LazyClock signal output during `suspend' state. For details about the DC's interrupt logic, see Section 8.6.3. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 107 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller hardware configuration register CLKRUN SUSPEND . . . CKDIV[3:0] enable XTAL OSC 4 6 MHz enable 48 MHz PLL 8x / (N + 1) N 1 CLKOUT 0 NOLAZY . . . NOLAZY LAZYCLOCK 100 (50%) kHz enable MGS775 Fig 47. Oscillator and LazyClock logic. When ISP1161A's DC enters `suspend' state (by setting and clearing bit GOSUSP in the DcMode Register), outputs D_SUSPEND and CLKOUT change state after approximately 2 ms delay. When NOLAZY = 0 the clock signal on output CLKOUT does not stop, but changes to the 100 50% kHz LazyClock frequency. When resuming from `suspend' state by a positive pulse on input D_WAKEUP, output SUSPEND is cleared and the clock signal on CLKOUT restarted after a 0.5 ms delay. The timing of the CLKOUT signal at `suspend' and `resume' is given in Figure 48. GOSUSP D_WAKEUP 1.8 to 2.2 ms D_SUSPEND PLL circuit stable 3 to 4 ms CLKOUT 004aaa038 0.5 ms If enabled, the 100 50% kHz LazyClock frequency will be output on pin CLKOUT during `suspend' state. Fig 48. CLKOUT signal timing at `suspend' and `resume' for DC. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 108 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 17. Limiting values Table 111: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC(5V) VCC(3.3V) VI Ilatchup Vesd Tstg [1] Parameter supply voltage to VCC pin supply voltage to Vreg(3.3) pin input voltage latchup current electrostatic discharge voltage storage temperature Conditions Min -0.5 -0.5 -0.5 Max +6.0 +4.6 +6.0 100 2000 +150 Unit V V V mA V C VI < 0 or VI > VCC ILI < 1 A [1] -60 Equivalent to discharging a 100 pF capacitor via a 1.5 k resistor (Human Body Model). Table 112: Recommended operating conditions Symbol VCC VI VI(A I/O) VO(od) Tamb [1] Parameter supply voltage input voltage input voltage on analog I/O pins (D+ / D-) open-drain output pull-up voltage operating ambient temperature Conditions with internal regulator internal regulator bypass Min 4.0 3.0 0 0 0 -40 Typ 5.0 3.3 VCC - Max 5.5 3.6 5.5[1] 3.6 VCC +85 Unit V V V V V C 5 V tolerant. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 109 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 18. Static characteristics Table 113: Static characteristics; supply pins VCC = 3.0 to 3.6 V or 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol VCC = +5 V Vreg(3.3) ICC ICC(susp) ICC(HC) ICC(DC) VCC = +3.3 V ICC ICC(susp) ICC(HC) ICC(DC) [1] Parameter internal regulator output operating supply current suspend supply current Conditions Min 3.0[1] - Typ 3.3 47 40 22 18 50 150 22 18 Max 3.6 500 500 - Unit V mA A mA mA mA A mA mA operating supply current for HC DC is suspended operating supply current for DC HC is suspended operating supply current suspend supply current operating supply current for HC DC is suspended operating supply current for DC HC is suspended In `suspend' mode, the minimum voltage is 2.7 V. Table 114: Static characteristics: digital pins VCC = 3.0 to 3.6 V or 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Vtrip Input levels VIL VIH Vth(LH) Vth(HL) Vhys Output levels VOL VOH LOW-level output voltage HIGH-level output voltage IOL = 4 mA IOL = 20 A IOH = 4 mA IOH = 20 A Leakage current ILI CIN IOZ [1] [1] Parameter overcurrent detection trip voltage LOW-level input voltage HIGH-level input voltage positive-going threshold voltage negative-going threshold voltage hysteresis voltage Conditions Min Typ 75 Max Unit mV 2.0 1.4 0.9 0.4 2.4 Vreg(3.3) - 0.1 pin to GND - - 0.8 1.9 1.5 0.7 0.4 0.1 5 5 5 V V V V V V V V V A pF A Schmitt trigger inputs input leakage current pin capacitance OFF-state output current Not applicable for open-drain outputs. Open-drain outputs 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 110 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 115: Static characteristics: analog I/O pins (D+, D-) VCC = 3.0 to 3.6 V or 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Input levels VDI VCM VIL VIH Output levels VOL VOH ILZ Capacitance CIN Resistance RPD RPU ZDRV ZINP Termination VTERM termination voltage for upstream port pull-up (RPU) 3.0[3] 3.6 V pull-down resistance on HC's DP/DM pull-up resistance on D_DP driver output impedance input impedance enable internal resistors SoftConnect = ON steady-state drive [2] Parameter differential input sensitivity differential common mode voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage OFF-state leakage current transceiver capacitance Conditions |VI(D+) - VI(D-)| includes VDI range [1] Min 0.2 0.8 2.0 Typ - Max 2.5 0.8 0.3 3.6 10 10 20 2 44 - Unit V V V V V V A pF k k M RL = 1.5 k to +3.6 V RL = 15 k to GND 2.8 - Leakage current pin to GND 10 1 29 10 [1] [2] [3] D+ is the USB positive data pin; D- is the USB negative data pin. Includes external resistors of 18 1% on both H_D+ and H_D-. In `suspend mode', the minimum voltage is 2.7 V. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 111 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 19. Dynamic characteristics Table 116: Dynamic characteristics VCC = 3.0 to 3.6 V or 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Reset tW(RESET) pulse width on input RESET crystal oscillator running crystal oscillator stopped Crystal oscillator fXTAL [1] Parameter Conditions Min 50 - Typ [1] Max - Unit s ms crystal frequency - 6 - MHz Dependent on the crystal oscillator start-up time. Table 117: Dynamic characteristics: analog I/O pins (D+, D-)[1] VCC = 3.0 to 3.6 V or 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; CL = 50 pF; RPU = 1.5 k 5% on D+ to VTERM; unless otherwise specified. Symbol tFR Parameter rise time Conditions CL = 50 pF; 10 to 90% of |VOH - VOL| CL = 50 pF; 90 to 10% of |VOH - VOL| [2] Min 4 Typ - Max 20 Unit ns Driver characteristics tFF fall time 4 - 20 ns FRFM VCRS [1] [2] [3] differential rise/fall time matching (tFR/tFF) output signal crossover voltage 90 1.3 - 111.11 2.0 % V [2][3] Test circuit; see Figure 64. Excluding the first transition from Idle state. Characterized only, not tested. Limits guaranteed by design. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 112 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 19.1 Timing symbols Table 118: Legend for timing characteristics Symbol Time symbols t T Signal names A C D E G I L P Q R address; DMA acknowledge (DACK) clock; command data input; data chip enable output enable instruction (program memory content); input (general) address latch enable (ALE) program store enable (PSEN, active LOW); propagation delay data output read signal (RD, active LOW); read (action); DMA request (DREQ) S W chip select write signal (WR, active LOW); write (action); pulse width U Y Logic levels H L P S V X Z logic HIGH logic LOW stop, not active (OFF) start, active (ON) valid logic level invalid logic level high-impedance (floating, three-state) undefined output (general) time cycle time (periodic signal) Description 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 113 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 19.2 Programmed I/O timing * If you are accessing only the HC, then the HC Programmed I/O timing applies. * If you are accessing only the DC, then the DC Programmed I/O timing applies. * If you are accessing both the HC and the DC, then the DC Programmed I/O timing applies. 19.2.1 HC Programmed I/O timing Table 119: Dynamic characteristics: HC Programmed interface timing Symbol tAS tAH read timing tSHSL tSLRL tRHSH tRLRH tRHRL TRC tRHDZ tRLDV write timing tWL tWHWL TWC tSLWL tWHSH tWDSU tWDH WR LOW pulse width WR HIGH to next WR LOW WR cycle time CS LOW to WR LOW WR HIGH to CS HIGH WR data set-up time WR data hold time 26 110 136 0 0 5 8 ns ns ns ns ns ns ns first RD/WR after A0 HIGH CS LOW to RD LOW RD HIGH to CS HIGH RD LOW pulse width RD HIGH to next RD LOW RD cycle time RD data hold time RD LOW to data valid 300 0 0 33 110 143 3 32 22 ns ns ns ns ns ns ns ns Parameter address set-up time before CS HIGH address hold time after CS HIGH Conditions Min 5 8 Typ Max Unit ns ns 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 114 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller CS t SHSL A0 tAS t RLRH t SLRL t SLWL t RHSH t RHRL AH T RC t WHSH t RD t RLDV D [15:0] data valid t WL WR t WDH D [15:0] data valid data valid data valid t WDSU data valid data valid MGT969 t RHDZ data valid t WHWL TWC data valid data valid Fig 49. HC Programmed interface timing 19.2.2 DC Programmed I/O timing Table 120: Dynamic characteristics: DC Programmed interface timing Symbol tRHAX tAVRL tSHDZ tRLRH tRLDV tSHRL tWHAX tAVWL tSHWL tWLWH tWHSH tDVWH tWHDZ [1] [2] Parameter address hold time after RD HIGH address set-up time before RD LOW data outputs high-impedance time after CS HIGH RD pulse width data valid time after RD LOW read interval after CS HIGH[1] address hold time after WR HIGH address set-up time before WR LOW write interval after CS HIGH[2] WR pulse width chip deselect time after WR HIGH data set-up time before WR HIGH data hold time after WR HIGH Conditions Min 3 0 25 180 3 0 180 22 0 5 3 Typ - Max 3 22 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns read timing (see Figure 50) write timing (see Figure 51) Measured from CS going HIGH to CS and RD both going LOW. Measured from CS going HIGH to CS and WR both going LOW. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 115 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller t RHAX A0 tAVRL t SHDZ CS/DACK2(2) t RLRH RD t RLDV D[15:0] 004aaa105 t SHRL(1) t RHSH (1) For tSHRL both CS and RD must be de-asserted. (2) Programmable polarity: shown as active LOW. Fig 50. DC Programmed interface read timing (I/O and 8237 compatible DMA). t WHAX A0 tAVWL CS/DACK2(2) t WLWH t SHWL(1) t WHSH WR t DVWH D[15:0] 004aaa106 t WHDZ (1) For tSHWL both CS and WR must be de-asserted. (2) Programmable polarity: shown as active LOW. Fig 51. DC Programmed interface write timing (I/O and 8237 compatible DMA). 19.3 DMA timing 19.3.1 HC single-cycle DMA timing Table 121: Dynamic characteristics: HC single-cycle DMA timing Symbol tRLRH tRLDV 9397 750 09568 Parameter RD pulse width read process data set-up time Conditions Min 33 26 Typ - Max - Unit ns ns read/write timing (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 116 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 121: Dynamic characteristics: HC single-cycle DMA timing...continued Symbol tRHDZ tWSU tWHD tAHRH tALRL TDC tSHAH tRHAL tDS [1] Parameter read process data hold time write process data set-up time write process data hold time DACK1 HIGH to DREQ1 HIGH DACK1 LOW to DREQ1 LOW DREQ1 cycle RD/WR HIGH to DACK1 HIGH DREQ1 HIGH to DACK1 LOW DREQ1 pulse spacing Conditions Min 0 5 0 72 [1] Typ - Max 20 21 - Unit ns ns ns ns ns ns ns ns ns 0 0 146 tRHAL + tDS +tALRL. T DC DREQ1 t DS t ALRL t RHAL DACK1 t AHRH t RLDV D [15:0] (read) data valid t RHDZ t SHAH D [15:0] (write) data valid t WSU RD or WR t WHD 004aaa107 Fig 52. HC single-cycle DMA timing. 19.3.2 HC burst mode DMA timing Table 122: Dynamic characteristics: HC burst mode DMA timing Symbol Parameter tRLRH tRHRL TRC tSLRL tSHAH tSLAL 9397 750 09568 Conditions Min 42 60 102 22 0 0 Typ - Max 64 - Unit ns ns ns ns ns ns read/write timing (for 4-cycle and 8-cycle burst mode) WR/RD LOW pulse width WR/RD HIGH to next WR/RD LOW WR/RD cycle RD/WR LOW to DREQ1 LOW RD/WR HIGH to DACK1 HIGH DREQ1 HIGH to DACK1 LOW (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 117 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Table 122: Dynamic characteristics: HC burst mode DMA timing...continued Symbol Parameter TDC tDS(read) tDS(write) tRLIS [1] Conditions 4-cycle burst mode 8-cycle burst mode 4-cycle burst mode 8-cycle burst mode Min [1] Typ - Max - Unit ns ns ns ns ns ns DREQ1 cycle DREQ1 pulse spacing (read) DREQ1 pulse spacing (write) RD/WR LOW to EOT LOW 105 150 72 167 0 tSLAL + (4 or 8)tRC + tDS. t DS DREQ1 t RHSH t RHAL DACK1 t RHRL t RL RD or WR 004aaa108 t SLRL t SHAH T RC Fig 53. HC burst mode DMA timing. 19.3.3 External EOT timing for HC single-cycle DMA DREQ1 DACK1 RD or WR EOT t RLIS > 0 ns 004aaa109 Fig 54. External EOT timing for HC single-cycle DMA. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 118 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 19.3.4 External EOT timing for HC burst mode DMA DREQ1 DACK1 RD or WR EOT t RLIS > 0 ns 004aaa110 Fig 55. External EOT timing for HC burst mode DMA. 19.3.5 DC single-cycle DMA timing (8237 mode) Table 123: Dynamic characteristics: DC single-cycle DMA timing (8237 mode) Symbol tASRP Tcy(DREQ2) Parameter DREQ2 off after DACK2 on cycle time signal DREQ2 Conditions Min 180 Typ Max 40 Unit ns ns T RC t ASRP DREQ2 DACK2(1) 004aaa111 (1) Programmable polarity: shown as active LOW. Fig 56. DC single-cycle DMA timing (8237 mode). 19.3.6 DC single-cycle DMA read timing in DACK-only mode Table 124: Dynamic characteristics: DC single-cycle DMA read timing in DACK-only mode Symbol tASRP tASAP tASAP + tAPRS tASDV tAPDZ Parameter DREQ off after DACK on DACK pulse width DREQ on after DACK off data valid after DACK on data hold after DACK off Conditions Min 25 180 Typ Max 40 22 3 Unit ns ns ns ns ns 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 119 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller t ASRP DREQ2 t ASAP DACK2(1) t APRS t ASDV DATA t APDZ 004aaa112 (1) Programmable polarity: shown as active LOW. Fig 57. DC single-cycle DMA read timing in DACK-only mode. 19.3.7 DC single-cycle DMA write timing in DACK-only mode Table 125: Dynamic characteristics: DC single-cycle DMA write timing in DACK-only mode Symbol tASRP tASAP + tAPRS tDVAP tAPDZ Parameter DREQ2 off after DACK2 on DREQ2 on after DACK2 off data setup before DACK2 off data hold after DACK2 off Conditions Min 180 5 3 Typ Max 40 Unit ns ns ns ns t ASAP t ASRP DREQ2 t APRS t DVAP DACK2(1) t APDZ DATA 004aaa113 (1) Programmable polarity: shown as active LOW. Fig 58. DC single-cycle DMA write timing in DACK-only mode. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 120 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 19.3.8 EOT timing in DC single-cycle DMA Table 126: Dynamic characteristics: EOT timing in DC single-cycle DMA Symbol tRSIH tIHAP tEOT Parameter input RD/WR HIGH after DREQ on DACK off after input RD/WR HIGH EOT pulse width EOT on; DACK on; RD/WR LOW Conditions Min 22 0 22 Typ Max Unit ns ns ns tRLIS tWLIS input EOT on after RD LOW input EOT on after WR LOW - - 89 89 ns ns t RSIH DREQ2 t ASRP (1) t IHAP DACK2 (4) RD/WR (2) t RLIS tWLIS EOT (4) t EOT (3) 004aaa114 (1) tASRP starts from DACK or RD/WR going LOW, whichever occurs later. (2) The RD/WR signals are not used in DACK-only DMA mode. (3) The EOT condition is considered valid if DACK, RD/WR and EOT are all active (= LOW). (4) Programmable polarity: shown as active LOW. Fig 59. EOT timing in DC single-cycle DMA. 19.3.9 DC burst mode DMA timing Table 127: Dynamic characteristics: DC burst mode DMA timing Symbol tRSIH tILRP tIHAP tIHIL Parameter input RD/WR HIGH after DREQ on DREQ off after input RD/WR LOW DACK off after input RD/WR HIGH DMA burst repeat interval (input RD/WR HIGH to LOW) Conditions Min 22 0 180 Typ Max 60 Unit ns ns ns ns 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 121 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller t RSIH DREQ2 t ILRP t IHAP DACK2(1) t IHIL RD/WR 004aaa115 (1) Programmable polarity: shown as active LOW. Fig 60. DC burst mode DMA timing. 19.3.10 EOT timing in DC burst mode DMA Table 128: Dynamic characteristics: EOT timing in DC burst mode DMA Symbol tEOT Parameter EOT pulse width Conditions EOT on; DACK on; RD/WR LOW Min 22 Typ Max Unit ns tISRP tRLIS tWLIS DREQ off after input EOT on input EOT on after RD LOW input EOT on after WR LOW - - 40 89 89 ns ns ns t ISRP DREQ2 DACK2(2) t RLIS tWLIS RD/WR t EOT(1) EOT(2) 004aaa116 (1) The EOT condition is considered valid if DACK2, RD/WR and EOT are all active (= LOW). (2) Programmable polarity: shown as active LOW. Fig 61. EOT timing in DC burst mode DMA. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 122 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 20. Application information 20.1 Typical interface circuit +5 V + 3.3 V VDD + 5 V + 3.3 V +5 V MOSFET (2x) (1) SH7709 + 3.3 V +5 V D [15:0] A1 A2 CS5 RD RD/WR DREQ0 DACK0 DREQ1 DACK1 ISP1161A VCC D [15:0] A0 A1 CS RD WR DREQ1 DACK1 DREQ2 DACK2 EOT H_OC1 H_OC2 H_PSW2 H_PSW1 H_DM1 H_DP1 H_DM2 H_DP2 D_DM D_DP Vreg Vreg(3.3) + 3.3 V FB3 22 (2x) VDD VDD LED (2) Vbus_DN2 Vbus_DN1 22 (2x) FB1 USB downstream port #1 47 pF (2x) FB2 +5 V CLKOUT EXTAL IRQ2 IRQ3 PTC0 PTC1 PTC2 PTC3 INT1 INT2 H_WAKEUP H_SUSPEND D_WAKEUP D_SUSPEND Vhold1 Vhold2 USB downstream port #2 XTAL 47 pF (2x) FB4 NDP_SEL EXTAL2 32 kHz XTAL2 RSTOUT RESET GL D_VBUS CLKOUT XTAL2 XTAL1 GND 6 MHz 22 pF 22 pF CLKOUT 470 Vbus_UP FB5 Vreg 22 (2x) 1.5 k USB upstream port FB6 47 pF (2x) 004aaa100 7 DGND AGND (1) For MOSFET, RDSon = 150 m. (2) 470 assuming that VCC is 5.0 V. Fig 62. Typical interface circuit to Hitachi SH-3 (SH7709) RISC processor. 20.2 Interfacing a ISP1161A with a SH7709 RISC processor This section shows a typical interface circuit between ISP1161A and a RISC processor. The Hitachi SH-3 series RISC processor SH7709 is used as the example. The main ISP1161A signals to be taken into consideration for connecting to a SH7709 RISC processor are: * A 16-bit data bus: D15-D0 for ISP1161A. ISP1161A is `little endian' compatible. * Two address lines A1 and A0 are needed for a complete addressing of the ISP1161A internal registers: - A1 = 0 and A0 = 0 will select the Data Port of the Host Controller - A1 = 0 and A0 = 1 will select the Command Port of the Host Controller - A1 = 1 and A0 = 0 will select the Data Port of the Device Controller 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 123 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller - A1 = 1 and A0 = 1 will select the Command Port of the Device Controller * The CS line is used for chip selection of ISP1161A in a certain address range of the RISC system. This signal is active LOW. * RD and WR are common read and write signals. These signals are active LOW. * There are two DMA channel standard control lines: - DREQ1 and DACK1 - DREQ2 and DACK2 (in each case one channel is used by the HC and the other channel is used by the DC). These signals have programmable active levels. * Two interrupt lines: INT1 (used by the host controller) and INT2 (used by the device controller). Both have programmable level/edge and polarity (active HIGH or LOW). * The internal 15 k pull-down resistors are used for the HCs two USB downstream ports. * The RESET signal is active LOW. Remark: SH7709's system clock input is for reference only. Please refer to SH7709's specification for its actual use. ISP1161A can work under either +3.3 V or +5.0 V power supply; however, its internal core actually works at +3.3 V. When using +5 V as the power supply input, the internal DC/DC regulator will be bypassed. It is best to connect all four power supply pins (VCC, Vreg(3.3), Vhold1 and Vhold2) to the 3.3 V power supply (for more information see Section 15). All of the ISP1161A's I/O pins are +5 V-tolerant. This feature allows the ISP1161A the flexibility to be used in an embedded system under either a +3.3 V or a +5 V power supply. A typical SH7709 interface circuit is shown in Figure 62. 20.3 Typical software model This section shows a typical software requirement for an embedded system that incorporates ISP1161A. The software model for a digital still camera (DSC) is used as the example for illustration (as shown in Figure 63). Two components of system software are required to make full use of the features in ISP1161A: the host stack and the device stack. The device stack provides API directly to the application task for device function; the host stack provides API for Class driver and device driver, both of which provide API for application tasks for host function. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 124 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller MECHANISM CONTROL TASK IMAGE PROCESSING TASKS Application layer FILE MANAGEMENT PRINTER UI/CONTROL FILE TRANSFER OS DEVICE DRIVERS Class driver MASS STORAGE CLASS DRIVER PRINTING CLASS DRIVER HOST STACK ISP1161A HAL DEVICE STACK USB host/device stack PC USB Upstream Printer RISC ROM RAM ISP1161A LEN CONTROL Flash card Reader/ Writer USB Downstream 004aaa101 Digital Still Camera Fig 63. ISP1161A software model for DSC application. 21. Test information The dynamic characteristics of the analog I/O ports (D+ and D-) as listed in Table 117 were determined using the circuit shown in Figure 64. test point 22 D.U.T. 15 k CL 50 pF MGT967 Load capacitance: CL = 50 pF (full-speed mode). Speed: full-speed mode only: internal 1.5 k pull-up resistor on D_DP. Fig 64. Load impedance for D_DP and D_DM pins. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 125 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 22. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 49 33 32 ZE e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3) e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o o 12.15 12.15 11.85 11.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 Fig 65. LQFP64 (SOT314-2) package outline. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 126 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm SOT414-1 c y X 48 49 33 32 ZE A e E HE wM pin 1 index bp L 64 1 ZD bp D HD wM B vM B 16 17 detail X Lp A A2 A1 (A 3) e vM A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.23 0.13 c 0.20 0.09 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.4 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 0.64 0.36 0.64 0.36 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT414-1 REFERENCES IEC 136E06 JEDEC MS-026 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 Fig 66. LQFP64 (SOT414-1) package outline. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 127 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 23. Soldering 23.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 23.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C small/thin packages. 23.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 128 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 23.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 23.5 Package related soldering information Table 129: Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[4], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO [1] [2] Soldering method Wave not suitable not suitable[3] Reflow[2] suitable suitable suitable suitable suitable suitable not not recommended[4][5] recommended[6] [3] [4] [5] [6] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 24. Revision history Table 130: Revision history Rev Date 01 20020802 CPCN Description Product data; initial version. 9397 750 09568 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 129 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller 25. Data sheet status Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 26. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 28. Trademarks GoodLink -- is a trademark of Koninklijke Philips Electronics N.V. Hitachi -- is a trademark of Hitachi Ltd. SoftConnect -- is a trademark of Koninklijke Philips Electronics N.V. ARM -- is a registered trademark of ARM PLC. StrongARM -- is a registered trademark of ARM PLC. 27. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 09568 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 130 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 9 9.1 9.2 9.3 9.3.1 9.4 9.4.1 9.4.2 9.4.3 9.5 9.5.1 9.5.2 9.6 9.7 9.8 9.8.1 9.8.2 9.9 9.9.1 9.9.2 10 10.1 10.1.1 10.1.2 10.1.3 10.1.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . 11 PLL clock multiplier. . . . . . . . . . . . . . . . . . . . . 11 Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . 11 Analog transceivers . . . . . . . . . . . . . . . . . . . . 11 Philips Serial Interface Engine (SIE). . . . . . . . 11 SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . 11 GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Microprocessor bus interface. . . . . . . . . . . . . 12 Programmed I/O (PIO) addressing mode . . . . 12 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Control register access by PIO mode . . . . . . . 13 I/O port addressing . . . . . . . . . . . . . . . . . . . . . 13 Register access phases . . . . . . . . . . . . . . . . . 14 FIFO buffer RAM access by PIO mode . . . . . 16 FIFO buffer RAM access by DMA mode. . . . . 17 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . 18 HC's interrupt output pin (INT1) . . . . . . . . . . . 19 DC interrupt output pin (INT2) . . . . . . . . . . . . 20 USB host controller (HC). . . . . . . . . . . . . . . . . 22 HC's four USB states . . . . . . . . . . . . . . . . . . . 22 Generating USB traffic . . . . . . . . . . . . . . . . . . 22 PTD data structure . . . . . . . . . . . . . . . . . . . . . 24 PTD data header definition . . . . . . . . . . . . . . . 25 HC internal FIFO buffer RAM structure . . . . . 27 Partitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Data organization . . . . . . . . . . . . . . . . . . . . . . 29 Operation and C program example. . . . . . . . . 30 HC operational model . . . . . . . . . . . . . . . . . . . 33 Time domain behavior . . . . . . . . . . . . . . . . . . 34 Control transaction limitations. . . . . . . . . . . . . 36 Microprocessor loading. . . . . . . . . . . . . . . . . . 36 Internal pull-down resistors for downstream ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 OC detection and power switching control . . . 37 Using an internal OC detection circuit . . . . . . 37 Using an external OC detection circuit . . . . . . 38 Suspend and wake-up . . . . . . . . . . . . . . . . . . 39 HC suspended state . . . . . . . . . . . . . . . . . . . . 39 HC wake-up from suspended state . . . . . . . . 40 HC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 HC control and status registers . . . . . . . . . . . 42 HcRevision Register (R: 00H). . . . . . . . . . . . . 42 HcControl Register (R/W: 01H/81H). . . . . . . . 43 HcCommandStatus Register (R/W: 02H/82H) 44 HcInterruptStatus Register (R/W: 03H/83H). . 45 10.1.5 10.1.6 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.5 10.5.1 10.5.2 10.5.3 10.6 10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 10.6.6 10.6.7 11 11.1 11.1.1 11.1.2 11.2 11.2.1 11.2.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.4 11.4.1 11.4.2 11.4.3 HcInterruptEnable Register (R/W: 04H/84H) . HcInterruptDisable Register (R/W: 05H/85H) HC frame counter registers . . . . . . . . . . . . . . HcFmInterval Register (R/W: 0DH/8DH) . . . . HcFmRemaining Register (R: 0EH) . . . . . . . . HcFmNumber Register (R: 0FH) . . . . . . . . . . HcLSThreshold Register (R/W: 11H/91H) . . . HC Root Hub Registers . . . . . . . . . . . . . . . . . HcRhDescriptorA Register (R/W: 12H/92H) . HcRhDescriptorB Register (R/W: 13H/93H) . HcRhStatus Register (R/W: 14H/94H) . . . . . . HcRhPortStatus[1:2] Register (R/W [1]:15H/95H, [2]: 16H/96H) . . . . . . . . . . HC DMA and interrupt control registers . . . . . HcHardwareConfiguration Register (R/W: 20H/A0H) . . . . . . . . . . . . . . . . . . . . . . . HcDMAConfiguration Register (R/W: 21H/A1H) . . . . . . . . . . . . . . . . . . . . . . . HcTransferCounter Register (R/W: 22H/A2H) HcPInterrupt Register (R/W: 24H/A4H) . . . . HcPInterruptEnable Register (R/W: 25H/A5H) . . . . . . . . . . . . . . . . . . . . . . . HC miscellaneous registers . . . . . . . . . . . . . . HcChipID Register (R: 27H). . . . . . . . . . . . . . HcScratch Register (R/W: 28H/A8H) . . . . . . HcSoftwareReset Register (W: A9H) . . . . . . . HC buffer RAM control registers . . . . . . . . . . HcITLBufferLength Register (R/W: 2AH/AAH) HcATLBufferLength Register (R/W: 2BH/ABH) . . . . . . . . . . . . . . . . . . . . . . HcBufferStatus Register (R: 2CH) . . . . . . . . . HcReadBackITL0Length Register (R: 2DH). . HcReadBackITL1Length Register (R: 2EH). . HcITLBufferPort Register (R/W: 40H/C0H) . . HcATLBufferPort Register (R/W: 41H/C1H) . . USB device controller (DC). . . . . . . . . . . . . . . DC data transfer operation . . . . . . . . . . . . . . . IN data transfer. . . . . . . . . . . . . . . . . . . . . . . . OUT data transfer. . . . . . . . . . . . . . . . . . . . . . Device DMA transfer . . . . . . . . . . . . . . . . . . . DMA for IN endpoint (internal DC to external USB host). . . . . . . . . DMA for OUT endpoint (external USB host to internal DC). . . . . . . . . Endpoint descriptions. . . . . . . . . . . . . . . . . . . Endpoints with programmable FIFO size . . . . Endpoint access. . . . . . . . . . . . . . . . . . . . . . . Endpoint FIFO size . . . . . . . . . . . . . . . . . . . . Endpoint initialization . . . . . . . . . . . . . . . . . . . Endpoint I/O mode access . . . . . . . . . . . . . . . Special actions on control endpoints . . . . . . . Suspend and resume . . . . . . . . . . . . . . . . . . . Suspend conditions . . . . . . . . . . . . . . . . . . . . Resume conditions. . . . . . . . . . . . . . . . . . . . . Control bits in suspend and resume. . . . . . . . 46 48 49 49 50 51 52 52 53 55 56 58 62 62 63 64 65 66 67 67 68 68 69 69 69 70 71 71 72 72 74 74 74 74 75 75 75 76 76 76 77 78 78 79 79 79 81 82 (c) RKoninklijke Philips Electronics N.V 2002. All rights reserved. Product data Rev. 01 -- 02 August 2002 131 of 132 Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Contents, cont. 12 DC DMA transfer . . . . . . . . . . . . . . . . . . . . . . . 83 12.1 Selecting an endpoint for DMA transfer . . . . . 83 12.2 8237 compatible mode . . . . . . . . . . . . . . . . . . 84 12.3 DACK-only mode . . . . . . . . . . . . . . . . . . . . . . 85 12.4 End-Of-Transfer conditions . . . . . . . . . . . . . . . 86 12.4.1 Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . 86 12.4.2 Isochronous endpoints . . . . . . . . . . . . . . . . . . 87 13 DC commands and registers . . . . . . . . . . . . . 88 13.1 Initialization commands . . . . . . . . . . . . . . . . . 90 13.1.1 DcEndpointConfiguration Register (R/W: 30H-3FH/20H-2FH). . . . . . . . . . . . . . . 90 13.1.2 DcAddress Register (R/W: B7H/B6H) . . . . . . 91 13.1.3 DcMode Register (R/W: B9H/B8H). . . . . . . . . 91 13.1.4 DcHardwareConfiguration Register (R/W: BBH/BAH). . . . . . . . . . . . . . . . . . . . . . . 92 13.1.5 DcInterruptEnable Register (R/W: C3H/C2H). 94 13.1.6 DcDMAConfiguration Register (R/W: F1H/F0H) . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.7 DcDMACounter Register (R/W: F3H/F2H) . . . 96 13.1.8 Reset Device (F6H) . . . . . . . . . . . . . . . . . . . . 96 13.2 Data flow commands . . . . . . . . . . . . . . . . . . . 96 13.2.1 Write/Read Endpoint Buffer (R/W: 10H,12H-1FH/01H-0FH) . . . . . . . . . . . 96 13.2.2 DcEndpointStatus Register (R: 50H-5FH) . . . 98 13.2.3 Stall Endpoint/Unstall Endpoint (40H-4FH/80H-8FH) . . . . . . . . . . . . . . . . . . . 99 13.2.4 Validate Endpoint Buffer (R/W: 6FH/61H). . . . 99 13.2.5 Clear Endpoint Buffer (70H, 72H-7FH) . . . . . 99 13.2.6 DcEndpointStatusImage Register(D0H-DFH) 99 13.2.7 Acknowledge Setup (F4H) . . . . . . . . . . . . . . 100 13.3 General commands . . . . . . . . . . . . . . . . . . . 100 13.3.1 Read Endpoint Error Code (R: A0H-AFH) . . 100 13.3.2 Unlock Device (B0H). . . . . . . . . . . . . . . . . . . 102 13.3.3 DcScratch Register (R/W: B3H/B2H) . . . . . . 102 13.3.4 Read Frame Number (R: B4H) . . . . . . . . . . . 103 13.3.5 Read Chip ID (R: B5H) . . . . . . . . . . . . . . . . . 104 13.3.6 Read Interrupt Register (R: C0H) . . . . . . . . . 104 14 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 15 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 106 16 Crystal oscillator and LazyClock . . . . . . . . . 107 17 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . 109 18 Static characteristics. . . . . . . . . . . . . . . . . . . 110 19 Dynamic characteristics . . . . . . . . . . . . . . . . 112 19.1 Timing symbols. . . . . . . . . . . . . . . . . . . . . . . 113 19.2 Programmed I/O timing. . . . . . . . . . . . . . . . . 114 19.2.1 HC Programmed I/O timing . . . . . . . . . . . . . 114 19.2.2 DC Programmed I/O timing . . . . . . . . . . . . . 115 19.3 DMA timing . . . . . . . . . . . . . . . . . . . . . . . . . . 116 19.3.1 HC single-cycle DMA timing . . . . . . . . . . . . . 116 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 19.3.7 19.3.8 19.3.9 19.3.10 20 20.1 20.2 20.3 21 22 23 23.1 23.2 23.3 23.4 23.5 24 25 26 27 28 HC burst mode DMA timing . . . . . . . . . . . . . External EOT timing for HC single-cycle DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External EOT timing for HC burst mode DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC single-cycle DMA timing (8237 mode) . . DC single-cycle DMA read timing in DACK-only mode . . . . . . . . . . . . . . . . . . . . . DC single-cycle DMA write timing in DACK-only mode . . . . . . . . . . . . . . . . . . . . . EOT timing in DC single-cycle DMA. . . . . . . DC burst mode DMA timing . . . . . . . . . . . . . EOT timing in DC burst mode DMA . . . . . . . Application information . . . . . . . . . . . . . . . . Typical interface circuit . . . . . . . . . . . . . . . . . Interfacing a ISP1161A with a SH7709 RISC processor . . . . . . . . . . . . . . . . . . . . . . Typical software model . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 117 118 119 119 119 120 121 121 122 123 123 123 124 125 126 128 128 128 128 129 129 129 130 130 130 130 (c) Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 02 August 2002 Document order number: 9397 750 09568 |
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